|
|
| Line 1: |
Line 1: |
| The term '''high-κ dielectric''' refers to a material with a high [[dielectric constant]] κ (as compared to [[silicon dioxide]]). High-κ dielectrics are used in semiconductor manufacturing processes where they are usually used to replace a [[silicon dioxide]] gate dielectric or another dielectric layer of a device. The implementation of high-κ gate dielectrics is one of several strategies developed to allow further miniaturization of microelectronic components, colloquially referred to as extending [[Moore's Law]].
| | Nice to meet you, I am Marvella Shryock. For many years I've been working as a payroll clerk. For a while she's been in South Dakota. One of the extremely very best things in the world for me is to do aerobics and I've been performing it for fairly a whilst.<br><br>Here is my web site; std home test; [http://www.pponline.co.uk/user/miriamlinswkucrd Full Record], |
| | |
| ==Need for high-κ materials==
| |
| | |
| Silicon dioxide has been used as a gate oxide material for decades. As transistors have decreased in size, the thickness of the silicon dioxide gate dielectric has steadily decreased to increase the gate capacitance and thereby drive current, raising device performance. As the thickness scales below 2 [[Nanometer|nm]], leakage currents due to [[Quantum tunneling|tunneling]] increase drastically, leading to high power consumption and reduced device reliability. Replacing the silicon dioxide gate dielectric with a high-κ material allows increased gate capacitance without the associated leakage effects.
| |
| | |
| ===First principles===
| |
| | |
| The gate oxide in a [[MOSFET]] can be modeled as a parallel plate capacitor. Ignoring quantum mechanical and depletion effects from the [[silicon|Si]] substrate and gate, the [[capacitance]] ''C'' of this parallel plate [[capacitor]] is given by
| |
| : <math>C=\frac{\kappa\varepsilon_{0}A}{t} </math>
| |
| [[File:High-k.svg|frame|right|Conventional silicon dioxide gate dielectric structure compared to a potential high-k dielectric structure]] [[File:FET cross section.png|thumbnail|Cross-section of an N channel [[MOSFET]] transistor showing the gate oxide dielectric]]
| |
| | |
| Where
| |
| | |
| *''A'' is the capacitor area
| |
| *κ is the [[dielectric constant|relative dielectric constant]] of the material (3.9 for [[silicon dioxide]])
| |
| *ε<sub>0</sub> is the [[Vacuum permittivity|permittivity of free space]]
| |
| *''t'' is the thickness of the capacitor oxide insulator
| |
| | |
| Since leakage limitation constrains further reduction of ''t'', an alternative method to increase gate capacitance is alter κ by replacing silicon dioxide with a high-κ material. In such a scenario, a thicker gate oxide layer might be used which can reduce the [[subthreshold leakage|leakage current]] flowing through the structure as well as improving the gate dielectric [[Reliability engineering|reliability]].
| |
| | |
| ===Gate capacitance impact on drive current===
| |
| The drain current ''I<sub>D</sub>'' for a [[MOSFET]] can be written (using the gradual channel approximation) as
| |
|
| |
| :<math>I_{D,Sat} = \frac{W}{L} \mu\, C_{inv}\frac{(V_{G}-V_{th})^2}{2}</math>
| |
| | |
| Where
| |
| *''W'' is the width of the transistor channel
| |
| *''L'' is the channel length
| |
| *μ is the channel carrier mobility (assumed constant here)
| |
| *''C<sub>inv</sub>'' is the capacitance density associated with the gate dielectric when the underlying channel is in the inverted state
| |
| *''V<sub>G</sub>'' is the voltage applied to the transistor gate
| |
| *''V<sub>D</sub>'' is the voltage applied to the transistor drain
| |
| *''V<sub>th</sub>'' is the [[threshold voltage]]
| |
| | |
| The term ''V<sub>G</sub> − V<sub>th</sub>'' is limited in range due to reliability and room temperature operation constraints, since a too large ''V<sub>G</sub>'' would create an undesirable, high electric field across the oxide. Furthermore, ''V<sub>th</sub>'' cannot easily be reduced below about 200 mV, because leakage currents due to increased oxide leakage (that is, assuming high-κ dielectrics are not available) and [[subthreshold conduction]] raise stand-by power consumption to unacceptable levels. (See the industry roadmap,<ref>{{cite web|url = http://www.itrs.net/Links/2006Update/FinalToPost/04_PIDS2006Update.pdf|work = International Technology Roadmap for Semiconductors: 2006 Update|title = Process Integration, Devices, and Structures}}</ref> which limits threshold to 200 mV, and Roy ''et al.'' <ref name=Roy>
| |
| {{cite book
| |
| |author=Kaushik Roy, Kiat Seng Yeo
| |
| |title=Low Voltage, Low Power VLSI Subsystems
| |
| |year= 2004
| |
| |publisher=McGraw-Hill Professional
| |
| |isbn=0-07-143786-X
| |
| |url=http://books.google.com/?id=jXm4pNxCSCYC&printsec=frontcover&dq=subthreshold+mosfet+%22static+power%22
| |
| |nopp=true
| |
| |pages=Fig. 2.1, p. 44}}</ref>). Thus, according to this simplified list of factors, an increased ''I<sub>D,sat</sub>'' requires a reduction in the channel length or an increase in the gate dielectric capacitance.
| |
| | |
| ==Materials and considerations==
| |
| Replacing the silicon dioxide gate dielectric with another material adds complexity to the manufacturing process. Silicon dioxide can be formed by [[thermal oxidation|oxidizing]] the underlying silicon, ensuring a uniform, conformal oxide and high interface quality. As a consequence, development efforts have focused on finding a material with a requisitely high dielectric constant that can be easily integrated into a manufacturing process. Other key considerations include [[electronic band structure|band]] alignment to [[silicon]] (which may alter leakage current), film morphology, thermal stability, maintenance of a high [[electron mobility|mobility]] of charge carriers in the channel and minimization of electrical defects in the film/interface. Materials which have received considerable attention are [[hafnium silicate]], [[zirconium silicate]], [[hafnium dioxide]] and [[zirconium dioxide]], typically deposited using [[atomic layer deposition]].
| |
| | |
| It is expected that [[defect states]] in the high-k dielectric can influence its electrical properties. Defect states can be measured for example by using zero-bias thermally stimulated current, zero-temperature-gradient zero-bias thermally stimulated [[dark current spectroscopy|current spectroscopy]],<ref>{{cite journal|doi=10.1063/1.119590|title=Detection of defect states responsible for leakage current in ultrathin tantalum pentoxide (Ta[sub 2]O[sub 5]) films by zero-bias thermally stimulated current spectroscopy|year=1997|last1=Lau|first1=W. S.|last2=Zhong|first2=L.|last3=Lee|first3=Allen|last4=See|first4=C. H.|last5=Han|first5=Taejoon|last6=Sandler|first6=N. P.|last7=Chong|first7=T. C.|journal=Applied Physics Letters|volume=71|page=500|issue=4|bibcode = 1997ApPhL..71..500L }}</ref><ref>{{cite journal|doi=10.1063/1.2199590|title=Application of zero-temperature-gradient zero-bias thermally stimulated current spectroscopy to ultrathin high-dielectric-constant insulator film characterization|year=2006|last1=Lau|first1=W. S.|last2=Wong|first2=K. F.|last3=Han|first3=Taejoon|last4=Sandler|first4=Nathan P.|journal=Applied Physics Letters|volume=88|page=172906|issue=17|bibcode = 2006ApPhL..88q2906L }}</ref> or [[inelastic electron tunneling spectroscopy]] (IETS).
| |
| | |
| ==Use in industry==
| |
| The industry has employed [[silicon oxynitride|oxynitride]] gate dielectrics since the 1990s, wherein a conventionally formed silicon oxide dielectric is infused with a small amount of nitrogen. The nitride content subtly raises the dielectric constant and is thought to offer other advantages, such as resistance against dopant diffusion through the gate dielectric.
| |
| | |
| In early 2007, [[Intel]] announced the deployment of [[hafnium]]-based high-k dielectrics in conjunction with a metallic gate for components built on [[45 nanometer]] technologies, and has shipped it in the 2007 processor series codenamed [[Penryn (microarchitecture)|Penryn]].<ref>{{cite web|url=http://www.intel.com/technology/architecture-silicon/45nm-core2/index.htm |title=Intel 45nm High-k Silicon Technology Page |publisher=Intel.com |date= |accessdate=2011-11-08}}</ref><ref>[http://www.spectrum.ieee.org/oct07/5553 IEEE Spectrum: The High-k Solution]</ref> At the same time, [[IBM]] announced plans to transition to high-k materials, also hafnium-based, for some products in 2008. While not identified, the most likely dielectric used in such applications are some form of nitrided hafnium silicates (HfSiON). HfO<sub>2</sub> and HfSiO are susceptible to crystallization during dopant activation annealing. [[NEC]] Electronics has also announced the use of a HfSiON dielectric in their 55 nm ''UltimateLowPower'' technology.<ref>{{cite web|url=http://www.necel.com/process/en/lowpower_overview.html |title=UltimateLowPower Technology|Advanced Process Technology|Technology|NEC Electronics |publisher=Necel.com |date= |accessdate=2011-11-08}}</ref> However, even HfSiON is susceptible to trap-related leakage currents, which tend to increase with stress over device lifetime. This leakage effect becomes more severe as hafnium concentration increases. There is no guarantee however, that hafnium will serve as a de facto basis for future high-k dielectrics. The 2006 [[International Technology Roadmap for Semiconductors|ITRS]] roadmap predicted the implementation of high-k materials to be commonplace in the industry by 2010.
| |
| | |
| ==See also==
| |
| *[[Low-k dielectric]]
| |
| *[[Silicon germanium]]
| |
| *[[Silicon on insulator]]
| |
| | |
| ==References==
| |
| {{reflist}}
| |
| | |
| ==Further reading==
| |
| * [http://dx.doi.org/10.1063/1.1361065 Review article] by Wilk ''et al.'' in the [[Journal of Applied Physics]]
| |
| *Houssa, M. (Ed.) (2003) ''High-k Dielectrics'' Institute of Physics ISBN 0-7503-0906-7 [http://www.crcpress.com/shopping_cart/products/product_detail.asp?sku=IP365 CRC Press Online]
| |
| *Huff, H.R., Gilmer, D.C. (Ed.) (2005) ''High Dielectric Constant Materials : VLSI MOSFET applications'' Springer ISBN 3-540-21081-4
| |
| *Demkov, A.A, Navrotsky, A., (Ed.) (2005) ''Materials Fundamentals of Gate Dielectrics'' Springer ISBN 1-4020-3077-0
| |
| *"High dielectric constant gate oxides for metal oxide Si transistors" Robertson, J. (''Rep. Prog. Phys.'' '''69''' 327-396 2006) ''Institute Physics Publishing'' [http://dx.doi.org/10.1088/0034-4885/69/2/R02 High dielectric constant gate oxides]
| |
| *Media coverage of March, 2007 Intel/IBM announcements [http://news.bbc.co.uk/1/hi/technology/6299147.stm BBC NEWS|Technology|Chips push through nano-barrier], [http://www.nytimes.com/2007/01/27/technology/27chip.html NY Times Article (1/27/07)]
| |
| *Gusev, E. P. (Ed.) (2006) "Defects in High-k Gate Dielectric Stacks: Nano-Electronic Semiconductor Devices", Springer ISBN 1-4020-4366-X
| |
| | |
| {{DEFAULTSORT:High-k dielectric}}
| |
| [[Category:Electronic engineering]]
| |
| [[Category:Transistors]]
| |
| [[Category:High-k dielectrics|*]]
| |
| [[Category:Semiconductor device materials]]
| |
Nice to meet you, I am Marvella Shryock. For many years I've been working as a payroll clerk. For a while she's been in South Dakota. One of the extremely very best things in the world for me is to do aerobics and I've been performing it for fairly a whilst.
Here is my web site; std home test; Full Record,