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| A '''logic gate''' is an idealized or physical device implementing a [[Boolean function]], that is, it performs a [[logical operation]] on one or more logical inputs, and produces a single logical output. Depending on the context, the term may refer to an '''ideal logic gate''', one that has for instance zero [[rise time]] and unlimited [[fan-out]], or it may refer to a non-ideal physical device<ref>Jaeger, Microelectronic Circuit Design, McGraw-Hill 1997, ISBN 0-07-032482-4, pp. 226-233</ref> (see [[Ideal and real op-amps]] for comparison).
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| Logic gates are primarily implemented using [[diode]]s or [[transistor]]s acting as [[switch#Electronic switches|electronic switches]], but can also be constructed using electromagnetic [[relay]]s ([[relay logic]]), [[fluidic logic]], [[pneumatics#Pneumatic logic|pneumatic logic]], [[optics]], [[molecular logic gate|molecules]], or even [[analytical engine|mechanical]] elements. With amplification, logic gates can be cascaded in the same way that Boolean functions can be composed, allowing the construction of a physical model of all of [[Boolean logic]], and therefore, all of the algorithms and [[mathematics]] that can be described with Boolean logic.
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| Logic circuits include such devices as [[multiplexer]]s, [[processor register|registers]], [[arithmetic logic unit]]s (ALUs), and [[computer storage|computer memory]], all the way up through complete [[microprocessor]]s, which may contain more than 100 million gates. In practice, the gates are made from [[field-effect transistor]]s (FETs), particularly [[MOSFET]]s (metal–oxide–semiconductor field-effect transistors).
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| Compound logic gates [[AND-OR-Invert]] (AOI) and OR-AND-Invert (OAI) are often employed in circuit design because their construction using MOSFETs is simpler and more efficient than the sum of the individual gates.<ref>{{cite book |title=Engineering digital design: Revised Second Edition |last = Tinder |first=Richard F. |year=2000 |isbn=0-12-691295-5 |pages=317–319 |url=http://books.google.com/?id=6x0pjjMKRh0C&pg=PT347&lpg=PT347&dq=AOI+gate#PPT346,M1 |accessdate=2008-07-04}}</ref>
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| In [[Reversible computing|reversible logic]], [[Toffoli gate]]s are used.
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| == Electronic gates ==
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| {{Main| Logic family }}
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| To build a [[functionally complete]] logic system, [[relay]]s, [[thermionic valve|valves]] (vacuum tubes), or [[transistor]]s can be used. The simplest family of logic gates using [[bipolar transistors]] is called [[resistor-transistor logic]] (RTL). Unlike diode logic gates, RTL gates can be cascaded indefinitely to produce more complex logic functions. These gates were used in early [[integrated circuit]]s. For higher speed, the resistors used in RTL were replaced by diodes, leading to [[diode-transistor logic]] (DTL). [[Transistor-transistor logic]] (TTL) then supplanted DTL with the observation that one transistor could do the job of two diodes even more quickly, using only half the space. In virtually every type of contemporary chip implementation of digital systems, the bipolar transistors have been replaced by complementary [[field-effect transistor]]s ([[MOSFET]]s) to reduce size and power consumption still further, thereby resulting in complementary metal–oxide–semiconductor ([[CMOS]]) logic.
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| For small-scale logic, designers now use prefabricated logic gates from families of devices such as the [[Transistor-transistor logic|TTL]] [[7400 series]] by [[Texas Instruments]] and the [[CMOS]] [[4000 series]] by [[RCA]], and their more recent descendants. Increasingly, these fixed-function logic gates are being replaced by [[programmable logic device]]s, which allow designers to pack a large number of mixed logic gates into a single [[integrated circuit]]. The field-programmable nature of [[programmable logic device]]s such as [[Field-Programmable Gate Array|FPGA]]s has removed the 'hard' property of hardware; it is now possible to change the logic design of a hardware system by reprogramming some of its components, thus allowing the features or function of a hardware implementation of a logic system to be changed.
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| Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consume much less power, and are much smaller (all by a factor of a million or more in most cases). Also, there is a fundamental structural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction) between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-[[gain]] [[voltage]] [[electronic amplifier|amplifier]], which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for current to flow between the output and the input of a semiconductor logic gate.
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| Another important advantage of standardized [[integrated circuit]] logic families, such as the 7400 and 4000 families, is that they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several other gates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer for the internal workings of the gates, provided the limitations of each [[integrated circuit]] are considered.
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| The output of one gate can only drive a finite number of inputs to other gates, a number called the '[[fanout]] limit'. Also, there is always a delay, called the '[[propagation delay]]', from a change in input of a gate to the corresponding change in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individual delays, an effect which can become a problem in high-speed circuits. Additional delay can be caused when a large number of inputs are connected to an output, due to the distributed [[capacitance]] of all the inputs and wiring and the finite amount of current that each output can provide.
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| == Symbols ==
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| [[File:74LS192 Symbol.png|thumb|right| A synchronous 4-bit up/down decade counter symbol (74LS192) in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication 60617-12.]]
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| There are two sets of symbols for elementary logic gates in common use, both defined in [[American National Standards Institute|ANSI]]/[[Institute of Electrical and Electronics Engineers|IEEE]] Std 91-1984 and its supplement ANSI/IEEE Std 91a-1991. The "distinctive shape" set, based on traditional schematics, is used for simple drawings, and derives from MIL-STD-806 of the 1950s and 1960s. It is sometimes unofficially described as "military", reflecting its origin. The "rectangular shape" set, based on [[International Electrotechnical Commission|IEC]] 60617-12 and other early industry standards, has rectangular outlines for all types of gate and allows representation of a much wider range of devices than is possible with the traditional symbols.<ref name="sdyz001a">''[http://www.ti.com/lit/ml/sdyz001a/sdyz001a.pdf Overview of IEEE Standard 91-1984 Explanation of Logic Symbols]'', Doc. No. SDYZ001A, Texas Instruments Semiconductor Group, 1996</ref> The IEC's system has been adopted by other standards, such as [[European Committee for Standardization|EN]] 60617-12:1999 in Europe and [[British Standard|BS]] EN 60617-12:1999 in the United Kingdom.
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| The goal of IEEE Std 91-1984 was to provide a uniform method of describing the complex logic functions of digital circuits with schematic symbols. These functions were more complex than simple AND and OR gates. They could be medium scale circuits such as a 4-bit counter to a large scale circuit such as a microprocessor. IEC 617-12 and its successor IEC 60617-12 do not explicitly show the "distinctive shape" symbols, but do not prohibit them.<ref name="sdyz001a" /> These are, however, shown in ANSI/IEEE 91 (and 91a) with this note: "The distinctive-shape symbol is, according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard." This compromise was reached between the respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance with one another.
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| A third style of symbols was in use in Europe and is still preferred by some, see the column "DIN 40700" in [[:de:Logikgatter#Typen von Logikgattern und Symbolik|the table in the German Wikipedia]].
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| In the 1980s, schematics were the predominant method to design both [[circuit boards]] and custom ICs known as [[gate array]]s. Today custom ICs and the [[field-programmable gate array]] are typically designed with [[Hardware description language|Hardware Description Languages]] (HDL) such as [[Verilog]] or [[VHDL]].
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| {| class="wikitable"
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| |-
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| ! Type !! Distinctive shape !! Rectangular shape !! Boolean algebra between A & B !! Truth table
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| |-
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| | '''[[AND gate|AND]]'''
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| | [[File:AND ANSI.svg|AND symbol]]
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| | [[File:AND IEC.svg|AND symbol]]
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| | <math>A \cdot B</math> or <math>A</math> <big>&</big> <math>B</math>
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| {| class="wikitable" style="float:right;"
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| |- style="background:#def; text-align:center;"
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| |colspan=2|'''INPUT''' || '''OUTPUT'''
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| |- style="background:#def; text-align:center;"
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| | A || B || A AND B
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| |- style="background:#dfd; text-align:center;"
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| |0 || 0 || 0
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| |- style="background:#dfd; text-align:center;"
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| |0 || 1 || 0
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| |- style="background:#dfd; text-align:center;"
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| |1 || 0 || 0
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| |- style="background:#dfd; text-align:center;"
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| |1 || 1 || 1
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| |}
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| |-
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| | '''[[OR gate|OR]]'''
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| | [[File:OR ANSI.svg|OR symbol]]
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| | [[File:OR IEC.svg|OR symbol]]
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| | <math>A+B</math>
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| {| class="wikitable" style="float:right;"
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| |- style="background:#def; text-align:center;"
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| |colspan=2|'''INPUT''' || '''OUTPUT'''
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| |- style="background:#def; text-align:center;"
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| | A || B || A OR B
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| |- style="background:#dfd; text-align:center;"
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| |0 || 0 || 0
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| |- style="background:#dfd; text-align:center;"
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| |0 || 1 || 1
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| |- style="background:#dfd; text-align:center;"
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| |1 || 0 || 1
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| |- style="background:#dfd; text-align:center;"
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| |1 || 1 || 1
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| |}
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| |-
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| | '''[[NOT gate|NOT]]'''
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| | [[File:NOT ANSI.svg|NOT symbol]]
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| | [[File:NOT IEC.svg|NOT symbol]]
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| | <math>\overline{A}</math> or <big>~</big><math>A</math>
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| {| class="wikitable" style="float:right;"
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| |- style="background:#def; text-align:center;"
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| |'''INPUT''' || '''OUTPUT'''
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| |- style="background:#def; text-align:center;"
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| | A || NOT A
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| |- style="background:#dfd; text-align:center;"
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| |0 || 1
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| |- style="background:#dfd; text-align:center;"
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| |1 || 0
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| |}
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| |-
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| | colspan="5" |In electronics a NOT gate is more commonly called an inverter. The circle on the symbol is called a ''bubble'', and is used in logic diagrams to indicate a logic negation between the external logic state and the internal logic state (1 to 0 or vice versa). On a circuit diagram it must be accompanied by a statement asserting that the ''positive logic convention'' or ''negative logic convention'' is being used (high voltage level = 1 or high voltage level = 0, respectively). The ''wedge'' is used in circuit diagrams to directly indicate an active-low (high voltage level = 0) input or output without requiring a uniform convention throughout the circuit diagram. This is called ''Direct Polarity Indication''. See IEEE Std 91/91A and IEC 60617-12. Both the ''bubble'' and the ''wedge'' can be used on distinctive-shape and [[rectangle|rectangular]]-shape symbols on circuit diagrams, depending on the logic convention used. On pure logic diagrams, only the ''bubble'' is meaningful.
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| |-
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| | '''[[NAND gate|NAND]]'''
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| | [[File:NAND ANSI.svg|NAND symbol]]
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| | [[File:NAND IEC.svg|NAND symbol]]
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| | <math>\overline{A \cdot B}</math> or <math>A | B</math>
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| {| class="wikitable" style="float:right;"
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| |- style="background:#def; text-align:center;"
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| |colspan=2|'''INPUT''' || '''OUTPUT'''
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| |- style="background:#def; text-align:center;"
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| | A || B || A NAND B
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| |- style="background:#dfd; text-align:center;"
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| |0 || 0 || 1
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| |- style="background:#dfd; text-align:center;"
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| |0 || 1 || 1
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| |- style="background:#dfd; text-align:center;"
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| |1 || 0 || 1
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| |- style="background:#dfd; text-align:center;"
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| |1 || 1 || 0
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| |}
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| |-
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| | '''[[NOR gate|NOR]]'''
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| | [[File:NOR ANSI.svg|NOR symbol]]
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| | [[File:NOR IEC.svg|NOR symbol]]
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| | <math>\overline{A + B}</math> or <math>A - B</math>
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| {| class="wikitable" style="float:right;"
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| |- style="background:#def; text-align:center;"
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| |colspan=2|'''INPUT''' || '''OUTPUT'''
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| |- style="background:#def; text-align:center;"
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| | A || B || A NOR B
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| |- style="background:#dfd; text-align:center;"
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| |0 || 0 || 1
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| |- style="background:#dfd; text-align:center;"
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| |0 || 1 || 0
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| |- style="background:#dfd; text-align:center;"
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| |1 || 0 || 0
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| |- style="background:#dfd; text-align:center;"
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| |1 || 1 || 0
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| |}
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| |-
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| | colspan="5" |
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| |-
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| | '''[[XOR gate|XOR]]'''
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| | [[File:XOR ANSI.svg|XOR symbol]]
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| | [[File:XOR IEC.svg|XOR symbol]]
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| | <math>A \oplus B</math>
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| {| class="wikitable" style="float:right;"
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| |- style="background:#def; text-align:center;"
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| |colspan=2|'''INPUT''' || '''OUTPUT'''
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| |- style="background:#def; text-align:center;"
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| | A || B || A XOR B
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| |- style="background:#dfd; text-align:center;"
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| |0 || 0 || 0
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| |- style="background:#dfd; text-align:center;"
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| |0 || 1 || 1
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| |- style="background:#dfd; text-align:center;"
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| |1 || 0 || 1
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| |- style="background:#dfd; text-align:center;"
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| |1 || 1 || 0
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| |}
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| |-
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| | '''[[XNOR gate|XNOR]]'''
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| | [[File:XNOR ANSI.svg|XNOR symbol]]
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| | [[File:XNOR IEC.svg|XNOR symbol]]
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| | <math>\overline{A \oplus B}</math> or <math>{A \odot B}</math>
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| {| class="wikitable" style="float:right;"
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| |- style="background:#def; text-align:center;"
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| |colspan=2|'''INPUT''' || '''OUTPUT'''
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| |- style="background:#def; text-align:center;"
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| | A || B || A XNOR B
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| |- style="background:#dfd; text-align:center;"
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| |0 || 0 || 1
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| |- style="background:#dfd; text-align:center;"
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| |0 || 1 || 0
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| |- style="background:#dfd; text-align:center;"
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| |1 || 0 || 0
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| |- style="background:#dfd; text-align:center;"
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| |1 || 1 || 1
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| |}
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| |}
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| Two more gates are the exclusive-OR or XOR function and its inverse, exclusive-NOR or XNOR. The two input Exclusive-OR is true only when the two input values are ''different'', false if they are equal, regardless of the value. If there are more than two inputs, the gate generates a true at its output if the number of trues at its input is ''odd'' ([http://www-inst.eecs.berkeley.edu/~cs61c/resources/dg-BOOL-handout.pdf]). In practice, these gates are built from combinations of simpler logic gates.
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| == Universal logic gates ==
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| {{details|functional completeness|the theoretical basis}}
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| [[File:7400.jpg|thumb|180px|The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.]]
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| [[Charles Sanders Peirce]] (winter of 1880–81) showed that [[NOR gates]] alone (or alternatively [[NAND gates]] alone) can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.<ref>Peirce, C. S. (manuscript winter of 1880–81), "A Boolean Algebra with One Constant", published 1933 in ''[[Charles Sanders Peirce bibliography#CP|Collected Papers]]'' v. 4, paragraphs 12–20. Reprinted 1989 in ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'' v. 4, pp. 218-21, Google [http://books.google.com/books?id=E7ZUnx3FqrcC&q=378+Winter Preview]. See Roberts, Don D. (2009), ''The Existential Graphs of Charles S. Peirce'', p. 131.</ref> The first published proof was by [[Henry M. Sheffer]] in 1913, so the NAND logical operation is sometimes called [[Sheffer stroke]]; the [[logical NOR]] is sometimes called ''Peirce's arrow''.<ref name="BüningLettmann1999">{{cite book|author1=Hans Kleine Büning|author2=Theodor Lettmann|title=Propositional logic: deduction and algorithms|url=http://books.google.com/books?id=3oJE9yczr3EC&pg=PA2|year=1999|publisher=Cambridge University Press|isbn=978-0-521-63017-7|page=2}}</ref> Consequently, these gates are sometimes called ''universal logic gates''.<ref name="Bird2007">{{cite book|author=John Bird|title=Engineering mathematics|url=http://books.google.com/books?id=1-fBmsEBNUoC&pg=PA532|year=2007|publisher=Newnes|isbn=978-0-7506-8555-9|page=532}}</ref>
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| == De Morgan equivalent symbols ==
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| By use of [[De Morgan's laws|De Morgan's theorem]], an ''AND'' function is identical to an ''OR'' function with negated inputs and outputs. Likewise, an ''OR'' function is identical to an ''AND'' function with negated inputs and outputs. A NAND gate is equivalent to an OR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs.
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| This leads to an alternative set of symbols for basic gates that use the opposite core symbol (''AND'' or ''OR'') but with the inputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and help to show accidental connection of an active high output to an active low input or vice-versa. Any connection that has logic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice-versa. Any connection that has a negation at one end and no negation at the other can be made easier to interpret by instead using the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both ends of a connection match, there is no logic negation in that path (effectively, bubbles "cancel"), making it easier to follow logic states from one symbol to the next. This is commonly seen in real logic diagrams - thus the reader must not get into the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles at both inputs and outputs in order to determine the "true" logic function indicated.
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| De Morgan's theorem is most commonly used to implement logic gates as combinations of only NAND gates, or as combinations of only NOR gates, for economic reasons.
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| == Data storage ==
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| {{Main|Sequential logic}}
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| Logic gates can also be used to store data. A storage element can be constructed by connecting several gates in a "[[Latch (electronics)|latch]]" circuit. More complicated designs that use [[clock signal]]s and that change only on a rising or falling edge of the clock are called edge-triggered "[[flip-flop (electronics)|flip-flop]]s". The combination of multiple flip-flops in parallel, to store a multiple-bit value, is known as a register. When using any of these gate setups the overall system has memory; it is then called a [[sequential logic]] system since its output can be influenced by its previous state(s).
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| These logic circuits are known as computer [[computer storage|memory]]. They vary in performance, based on factors of [[speed]], complexity, and reliability of storage, and many different types of designs are used based on the [[Function application|application]].
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| == Three-state logic gates ==
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| [[File:Tristate buffer.svg|thumb|320px|right|A tristate buffer can be thought of as a switch. If ''B'' is on, the switch is closed. If B is off, the switch is open.]]
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| {{Main|Tri-state buffer}}
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| A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are used on [[Bus (computing)|bus]]es of the [[Central Processing Unit|CPU]] to allow multiple chips to send data. A group of three-states driving a line with a suitable control circuit is basically equivalent to a [[multiplexer]], which may be physically distributed over separate devices or plug-in cards.
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| In electronics, a high output would mean the output is sourcing current from the positive power terminal (positive voltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). High impedance would mean that the output is effectively disconnected from the circuit.
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| == History and development ==
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| The [[binary number system]] was refined by [[Gottfried Wilhelm Leibniz]] (published in 1705) and he also established that by using the binary system, the principles of arithmetic and logic could be combined. In an 1886 letter, [[Charles Sanders Peirce]] described how logical operations could be carried out by electrical switching circuits.<ref name=P2M>Peirce, C. S., "Letter, Peirce to [[Allan Marquand|A. Marquand]]", dated 1886, ''[[Charles Sanders Peirce bibliography#W|Writings of Charles S. Peirce]]'', v. 5, 1993, pp. 541–3. Google [http://books.google.com/books?id=DnvLHp919_wC&q=Marquand Preview]. See [[Arthur W. Burks|Burks, Arthur W.]], "Review: Charles S. Peirce, ''The new elements of mathematics''", ''Bulletin of the American Mathematical Society'' v. 84, n. 5 (1978), pp. 913–18, see 917. [http://projecteuclid.org/DPubS/Repository/1.0/Disseminate?view=body&id=pdf_1&handle=euclid.bams/1183541145 PDF Eprint].</ref> Eventually, [[vacuum tube]]s replaced relays for logic operations. [[Lee De Forest]]'s modification, in 1907, of the [[vacuum tube|Fleming valve]] can be used as AND logic gate. [[Ludwig Wittgenstein]] introduced a version of the 16-row [[truth table]] as proposition 5.101 of ''[[Tractatus Logico-Philosophicus]]'' (1921). [[Walther Bothe]], inventor of the [[coincidence circuit]], got part of the 1954 [[Nobel Prize]] in physics, for the first modern electronic AND gate in 1924. [[Konrad Zuse]] designed and built electromechanical logic gates for his computer [[Z1 (computer)|Z1]] (from 1935–38). [[Claude E. Shannon]] introduced the use of Boolean algebra in the analysis and design of switching circuits in 1937. Active research is taking place in [[molecular logic gate]]s.
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| == Implementations ==
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| {{main|Unconventional computing}}
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| Since the 1990s, most logic gates are made in [[CMOS]] technology (i.e. NMOS and PMOS transistors are used). Often millions of logic gates are [[chip carrier|packaged]] in a single [[integrated circuit]].
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| There are several [[logic family|logic families]] with different characteristics (power consumption, speed, cost, size) such as: [[diode logic|RDL]] (resistor-diode logic), [[resistor-transistor logic|RTL]] (resistor-transistor logic), [[diode-transistor logic|DTL]] (diode-transistor logic), [[transistor-transistor logic|TTL]] (transistor-transistor logic) and [[CMOS]] (complementary metal oxide semiconductor). There are also sub-variants, e.g. standard CMOS logic vs. advanced types using still CMOS [[technology]], but with some optimizations for avoiding loss of [[speed]] due to slower PMOS transistors.
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| Non-electronic implementations are varied, though few of them are used in practical applications. Many early electromechanical digital computers, such as the [[Harvard Mark I]], were built from [[relay logic]] gates, using electro-mechanical [[relay]]s. Logic gates can be made using [[pneumatic]] devices, such as the [[Sorteberg relay]] or mechanical logic gates, including on a molecular scale.<ref>[http://www.zyvex.com/nanotech/mechano.html Mechanical Logic gates (focused on molecular scale)]</ref> Logic gates have been made out of [[DNA]] (see [[DNA nanotechnology]])<ref>[https://digamma.cs.unm.edu/wiki/bin/view/McogPublicWeb/MolecularLogicGates DNA Logic gates]</ref> and used to create a computer called MAYA (see [[MAYA II]]). Logic gates can be made from [[Quantum Mechanics|quantum mechanical]] effects (though [[quantum computing]] usually diverges from boolean design). [[Photonic logic]] gates use [[non-linear optics|non-linear optical]] effects.
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| == See also ==
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| {{div col|colwidth=30em}}
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| * [[And-inverter graph]]
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| * [[Boolean algebra topics]]
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| * [[Boolean function]]
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| * [[Digital circuit]]
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| * [[Minilog|Espresso heuristic logic minimizer]]
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| * [[Fanout]]
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| * [[Flip-flop (electronics)]]
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| * [[Functional completeness]]
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| * [[Karnaugh map]]
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| * [[Combinational logic]]
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| * [[Logic family]]
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| * [[Logical graph]]
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| * [[NMOS logic]]
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| * [[Propositional calculus]]
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| * [[Quantum gate]]
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| * [[Race hazard]]
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| * [[Reversible computing]]
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| * [[Truth table]]
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| {{div col end}}
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| ==References==
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| {{reflist}}
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| == Further reading ==
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| * {{cite book|last1=Awschalom|first1=D.D. |last2=Loss|first2=D.|last3=Samarth|first3=N.|title=Semiconductor Spintronics and Quantum Computation|url=http://books.google.com/books?id=tlDSx_8_5v4C|accessdate=28 November 2012|date=5 August 2002|publisher=Springer-Verlag|location=Berlin, Germany|isbn=978-3-540-42176-4}}
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| * {{cite book|last=Bostock|first=Geoff|title=Programmable logic devices: technology and applications|url=http://books.google.com/books?id=XEFTAAAAMAAJ|accessdate=28 November 2012|year=1988|publisher=McGraw-Hill|location=New York|isbn=978-0-07-006611-3}}
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| * {{cite book|last1=Brown|first1=Stephen D.|last2=Francis|first2=Robert J.|last3=Rose|first3=Jonathan|first4=Zvonko G.|last4=Vranesic|title=Field Programmable Gate Arrays|url=http://books.google.com/books?id=8s4M-qYOWZIC|accessdate=28 November 2012|year=1992|publisher=Kluwer Academic Publishers|location=Boston, MA|isbn=978-0-7923-9248-4}}
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| <!-- ==External links== -->
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| {{Digital systems}}
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| {{DEFAULTSORT:Logic Gate}}
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| [[Category:Logic gates| ]]
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