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{{about|Intel microprocessor architecture in general|the 32-bit generation of this architecture which is also called "x86"|IA-32}}
I'm Ouida and I live with my husband and our three children in Haslum, in the  south part. My hobbies are Golf, Games Club - Dungeons and Dragons, Monopoly, Etc. and Seaglass collecting.<br><br>Also visit my blog Fifa 15 Coin Generator ([http://editpass.80port.net/xe/?document_srl=147687 http://editpass.80port.net/])
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{{mergefrom|IA-32|discuss=Talk:IA-32#Get rid of it|date=January 2014}}
 
{{Infobox CPU architecture
| name      = x86
| designer  = [[Intel]], [[Advanced Micro Devices|AMD]]
| bits      = [[16-bit]], [[32-bit]] and/or [[64-bit]]
| introduced = 1978 (16-bit), 1985 (32-bit), 2003 (64-bit)
| version    =
| design    = [[Complex instruction set computing|CISC]]
| type      = Register-memory
| encoding  = Variable (1 to 15 bytes)
| branching  = [[Status register]]
| endianness = Little
| page size  = '''[[8086]]&ndash;[[i286]]''': None<br> '''[[Intel 386|i386]], [[Intel 486|i486]]''': 4&nbsp;KB pages<br>'''[[P5 (microarchitecture)|P5]] [[Pentium (brand)|Pentium]]''': added 4&nbsp;MB pages<br>(Legacy '''[[Physical Address Extension|PAE]]''': 4&nbsp;KB→2&nbsp;MB)<br> '''[[Long mode|x86-64]]''': added 1&nbsp;GB pages.
| extensions = [[x87]], [[IA-32]], [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[x86-64]], [[SSE3]], [[SSSE3]], [[SSE4]], [[SSE5]], [[Advanced Vector Extensions|AVX]]
| open      = Partly. For some advanced features, x86 may require license from Intel; x86-64 may require an additional license from AMD.  The 80486 processor has been on the market for more than 20 years<ref>80486 32-bit CPU breaks new ground in chip density and operating performance. (Intel Corp.) (product announcement) EDN | May 11, 1989 | Pryce, Dave</ref> and so cannot be subject to patent claims.  This subset of the x86 architecture is therefore fully open.
| gpr = '''16-bit''': 6<small> semi-dedicated registers</small> + BP and SP;<br/>'''32-bit''': 6<small> GPRs</small> + EBP and ESP;<br/>'''64-bit''': 14<small> GPRs</small> + RBP and RSP.
| fpr = '''16-bit''': Optional separate [[x87]] FPU.<br />'''32-bit''': Optional separate or integrated [[x87]] FPU, integrated [[SSE2]] units in later processors.<br />'''64-bit''': Integrated [[x87]] and [[SSE2]] units.
}}
 
[[Image:KL Intel D8086.jpg|thumb|The Intel 8086.]]
[[Image:Core 2 Duo E6300.jpg|thumb|Intel Core 2 Duo - an example of an x86-compatible, 64-bit multicore processor.]]
[[Image:Slot-A Athlon.jpg|thumb|AMD Athlon (early version) - another technically different, but fully compatible, x86 implementation.]]
The term '''x86''' denotes a family of [[backward compatible]] [[instruction set architecture]]s{{Efn|Unlike the [[microarchitecture]] (and specific electronic and physical implementation) used for a specific microprocessor design.}} based on the [[Intel 8086]] [[Central processing unit|CPU]]. The 8086 was introduced in 1978 as a fully [[16-bit]] extension of Intel's [[8-bit]] based [[Intel 8080|8080]] microprocessor, with [[x86 memory segmentation|memory segmentation]] as a solution for addressing more memory than can be covered by a plain 16-bit address. The term x86 derived from the fact that early successors to the 8086 also had names ending in "86".
 
Many additions and extensions have been added to the x86 instruction set over the years, almost consistently with full [[backward compatibility]].{{Efn|Intel abandoned its "x86" naming scheme with the ''[[P5 (microarchitecture)|P5]] [[Pentium (brand)|Pentium]]'' during 1993 (as ''numbers'' could not be trademarked). However, the term x86 was already established among technicians, compiler writers etc.}} The architecture has been implemented in processors from [[Intel Corporation|Intel]], [[Cyrix]], [[Advanced Micro Devices|AMD]], [[VIA Technologies|VIA]] and many other companies; there are also open implementations, such as the Zet [[System on a chip|SoC]] platform.<ref>{{cite web
| url = http://opencores.org/project,zet86
| title = Zet - The x86 (IA-32) open implementation :: Overview
| date = 2013-11-04 | accessdate = 2014-01-05
| publisher = opencores.org
}}</ref>
 
The term is not synonymous with [[IBM PC compatible|IBM PC compatibility]] as this implies a multitude of other [[computer hardware]]; [[embedded system]]s as well as general-purpose computers used x86 chips [[Influence of the IBM PC on the personal computer market#Before the IBM PC's introduction|before the PC-compatible market started]],{{Efn|the [[GRID Compass]] laptop, for instance}} some of them before the [[IBM PC]] itself.
 
''Note: In the following text, all instances of the prefixes kilo/mega/giga/tera are to be understood in the binary (powers of 2) sense. See the article on the ''[[Binary prefixes#IEC standard prefixes|IEC prefixes]]'' (kibi/mebi/gibi/tebi) for details.''
 
== Overview ==
In the 1980s and early 1990s when the [[8088]] and [[80286]] were still in common use, the term x86 usually represented any 8086 compatible CPU. Today, however, x86 usually implies a binary compatibility also with the [[32-bit]] [[instruction set]] of the 80386. This is due to the fact that this instruction set has become something of a lowest common denominator for many modern operating systems and probably also because the term became common ''after'' the introduction of the [[Intel 80386|80386]] in 1985.
 
The term ''x86'' sometimes may be emphasized as [[IA-32|x86-32]]<ref>{{cite web|url=http://www.oracle-base.com/articles/misc/Solaris10X86-32Installation.php |title=Solaris 10 (x86-32) Installation |publisher=Oracle-Base |date= |accessdate=2014-01-28}}</ref> to distinguish it either from the original 16-bit "x86-16" or from the [[64-bit]] [[x86-64]].{{Efn|Intel currently uses [[IA-32]] and [[Intel 64]] (formerly EM64T or IA-32e) for x86 and [[x86-64]] respectively.  Intel have used various names to market the successive generations of the architecture over the years: the name "iAPX 86" was originally used for the 8086 product family, and likewise the 80286 was the "iAPX 286".  Intel originally referred to the 80386 simply by that number (ca. 1986) before switching to the name "386 DX" (1990) and then "Intel386 DX" (1991).  The 80386 or x86-32 is sometimes denoted as [[i386]], often by [[GNU-Linux]] distributions. Likewise, AMD today prefers [[AMD64]] over the [[x86-64]] name it once introduced.}} Although most x86 processors used in ''new'' [[personal computer]]s and [[Server (computing)|server]]s have 64-bit capabilities, to avoid compatibility problems with older computers or systems, the term ''x86-64'' (or ''x64'') is often used to denote 64-bit software, with the term ''x86'' currently implying only 32-bit.<ref>{{cite web |title=Linux* Kernel Compiling |url=http://www.intel.com/cd/ids/developer/asmo-na/eng/182333.htm?page=4 |publisher=Intel |accessdate=2007-09-04 |archiveurl = http://web.archive.org/web/20070606034724/http://www.intel.com/cd/ids/developer/asmo-na/eng/182333.htm?page=4 <!-- Bot retrieved archive --> |archivedate = 2007-06-06}}</ref><ref>{{cite web |title=Intel Web page search result for "x64" |url=http://mysearch.intel.com/corporate/default.aspx?culture=en-US&q=x64&searchsubmit.x=21&searchsubmit.y=11 |accessdate=2007-09-04}}</ref>
 
Although the 8086 was primarily developed for [[embedded systems]] and small single-user computers, largely as a response to the successful 8080-compatible [[Zilog Z80]],<ref>[http://www.pcworld.com/article/146957/birth_of_a_standard_the_intel_8086_microprocessor.html Birth of a Standard: The Intel 8086 Microprocessor]</ref> the x86 line soon grew in features and processing power. Today, x86 is ubiquitous in both stationary and portable personal computers and has replaced  [[midrange computer]]s and Reduced instruction set computer ([[Reduced instruction set computer|RISC]]) based processors in a majority of servers and [[workstation]]s as well. A large amount of [[computer software|software]], including [[operating system]]s (OSs) such as [[DOS]], [[Microsoft Windows|Windows]], [[Linux]], [[BSD]], [[Solaris (operating system)|Solaris]] and [[Mac OS X]], functions with x86-based hardware.
 
Modern x86 is relatively uncommon in [[embedded systems]], however, and small [[Low-power electronics|low power]] applications (using tiny batteries) as well as low-cost microprocessor markets, such as [[home appliance]]s and toys, lack any significant x86 presence.{{Efn|The embedded processor market is populated by more than 25 different [[instruction set|architectures]], which, due to the price sensitivity, low power and hardware simplicity requirements, outnumber the x86.}} Simple 8-bit and 16-bit based architectures are common here, although the x86-compatible [[VIA C7]], [[VIA Nano]], [[Advanced Micro Devices|AMD]]'s [[Geode (processor)|Geode]], [[Athlon Neo]] and [[Intel Atom]] are examples of 32- and 64-bit designs used in some ''relatively'' low power and low cost segments.
 
There have been several attempts, including by Intel itself, to end the market dominance of the "inelegant" x86 architecture designed directly from the first simple 8-bit microprocessors. Examples of this are the [[iAPX 432]] (alias [[Intel 432|Intel 8800]]), the [[Intel 960]], [[Intel 860]] and the Intel/Hewlett-Packard [[Itanium]] architecture. However, the continuous refinement of x86 [[microarchitecture]]s, [[electronic circuit|circuitry]] and [[semiconductor manufacturing]] would make it hard to replace x86 in many segments. AMD's 64-bit extension of x86 (which Intel eventually responded to with a compatible design)<ref>[http://bwrc.eecs.berkeley.edu/CIC/announce/1999/k8.annc.html "Time and again, processor architects have looked at the inelegant x86 architecture and declared it cannot be stretched to accommodate the latest innovations," said Nathan Brookwood, principal analyst, Insight 64.]</ref> and the scalability of x86 chips such as the [[multi-core processor|eight-core]] Intel Xeon and 12-core AMD Opteron is underlining x86 as an example of how continuous refinement of established industry standards can resist the competition from completely new architectures.<ref>[http://www.eweek.com/c/a/IT-Infrastructure/Microsoft-to-End-Intel-Itanium-Support-370349/ Microsoft to End Intel Itanium Support]</ref>
 
==Chronology==
The table below lists brands of common<ref>{{cite web |title=Microprocessor Hall of Fame |url=http://www.intel.com/museum/online/hist%5Fmicro/hof/ |publisher=Intel |accessdate=2007-08-11 |archiveurl = http://web.archive.org/web/20070706032836/http://www.intel.com/museum/online/hist_micro/hof/ <!-- Bot retrieved archive --> |archivedate = 2007-07-06}}</ref> consumer targeted processors implementing the x86 [[instruction set]], grouped by generations that emphasize important events of x86 history. Note: CPU generations are not strict - each generation is characterized by significantly improved or commercially successful processor [[microarchitecture]] designs.
{| class="wikitable"
|-
! Generation
! First introduced
! Prominent consumer CPU brands
! Linear/physical address space
! Notable (new) features
|-
| rowspan="2" | 1 || 1978 || [[Intel 8086]], [[Intel 8088]] and clones || rowspan="2" | '''16-bit''' / 20-bit (segmented) || First x86 microprocessors
|-
| rowspan="2" | 1982 || [[Intel 80186]], [[Intel 80188]] and clones, [[NEC V20]]/V30 || Hardware for fast [[Memory address|address]] calculations, fast mul/div, etc.
|-
| 2 || [[Intel 80286]] and clones ||'''16-bit''' (30-bit virtual) / 24-bit (segmented)|| [[memory management unit|MMU]], for [[protected mode]] and a larger [[address space]].
|-
| 3 ([[IA-32]]) || 1985 || [[Intel 80386]] and clones, [[AMD Am386]] || rowspan="5" | '''32-bit''' (46-bit virtual) / 32-bit || [[32-bit]] [[instruction set]], MMU with paging.
|-
| 4 ([[Floating point unit|FPU]]) || 1989 || [[Intel 80486]] and clones, [[AMD Am486]]/[[Am5x86]] || RISC-like [[pipelining]], integrated [[x87]] [[Floating point unit|FPU]] (80-bit), on-chip [[CPU cache|cache]].
|-
| 4/5 || 1997 || [[Integrated Device Technology|IDT]]/[[Centaur Technology|Centaur]]-[[WinChip|C6]], [[Cyrix III]]-Samuel, [[VIA C3]]-Samuel2 / VIA C3-Ezra (2001), [[VIA C7]] (2005) || In-order, integrated FPU, some models with on-chip L2 cache, MMX, SSE.
|-
| 5 || 1993 || [[P5 (microarchitecture)|Pentium]], [[Pentium MMX]], [[Cyrix 5x86]], [[Rise Technology|Rise]] [[mP6]] || [[Superscalar]], [[64-bit]] [[Bus (computing)|databus]], faster FPU, [[MMX (instruction set)|MMX]] (2× 32-bit).
|-
| 5/6 || 1996 || [[AMD K5]], [[Nx586|Nx586 (1994)]]  || μ-op translation.
|-
| rowspan="3" | 6 || 1995 || [[Pentium Pro]], [[Cyrix 6x86]], [[Cyrix MII]], [[Cyrix III]]-Joshua (2000) || rowspan="6" | ''As above'' / '''36'''-bit physical ([[Physical Address Extension|PAE]])|| μ-op translation, conditional move instructions, [[Out-of-order execution|Out-of-order]], [[register renaming]], [[speculative execution]], [[Physical Address Extension|PAE]] (Pentium Pro), in-package [[L2 cache]] (Pentium Pro).
|-
| 1997 || [[AMD K6]]/[[AMD K6-2|-2/3]], [[Pentium II]]/[[Pentium III|III]] || L3-cache support, [[3DNow!]], [[Streaming SIMD Extensions|SSE]] (2× 64-bit).
|-
| 2003 || [[Pentium M]], [[Intel Core]] (2006)<!-- Intel Core is based off Pentium M --> || optimized for low [[Thermal Design Power|power]].
|-
| rowspan="2" | 7 || 1999 || [[Athlon]], [[Athlon XP]] || Superscalar FPU, wide design (up to three x86 instr./clock).
|-
| 2000 || [[Pentium 4]] || deeply [[pipelining|pipelined]], high frequency, [[SSE2]], [[hyper-threading]].
|-
| rowspan="4" | 7/8 || 2000 || [[Transmeta Crusoe]], [[Transmeta Efficeon]] || [[Very long instruction word|VLIW]] design with x86 [[emulator]], on-die memory controller.
|-
| 2004 || Pentium 4 [[Pentium4#Prescott|Prescott]] ||rowspan="4"|'''64-bit''' / 40-bit physical in first AMD implementation || Very deeply [[pipelining|pipelined]], very high frequency, [[SSE3]], 64-bit capability (integer CPU) is available only in LGA 775 sockets.
|-
| 2006 || [[Intel Core 2]] || 64-bit (integer CPU), low power, [[multi-core]], lower clock frequency, [[SSE4]] (Penryn).
|-
| 2008 || [[VIA Nano]] || [[Out-of-order execution|Out-of-order]], superscalar, 64-bit (integer CPU), [[hardware-based encryption]], very low power, adaptive [[power management]].
|-
| 8 ([[x86-64]]) || 2003 || [[Athlon 64]], [[Opteron]] || [[x86-64|x86-64 instruction set]] ([[Central processing unit|CPU]] main integer core), on-die memory controller, [[hypertransport]].
|-
| rowspan="4" | 8/9 || 2007 || AMD [[Phenom (processor)|Phenom]] || rowspan="4" | ''As above'' / 48-bit physical for AMD Phenom || rowspan="2" | Monolithic quad-core, [[SSE4a]], HyperTransport 3 or QuickPath, native memory controller, on-die L3 cache, modular.
|-
| rowspan="2" | 2008 || [[Intel Core]] i3/i5/i7, [[AMD Phenom II]]
|-
| [[Intel Atom]]|| In-order but highly pipelined, very-low-power, on some models: 64-bit (integer CPU), on-die GPU.
|-
| 2011 || AMD [[Bobcat (processor)|Bobcat]], [[AMD Fusion|Llano]] || [[Out-of-order execution|Out-of-order]], 64-bit (integer CPU), on-die GPU, low power (Bobcat).
|-
| rowspan="2"| 9 ([[Graphics processing unit|GPU]]) || 2011 || Intel [[Sandy Bridge (microarchitecture)|Sandy Bridge]]/[[Ivy Bridge (microarchitecture)|Ivy Bridge]], AMD [[Bulldozer (processor)|Bulldozer and Trinity]] || || [[SSE5]]/[[Advanced Vector Extensions|AVX]] (4× 64-bit), highly modular design, integrated on-die [[Graphics processing unit|GPU]].
|-
| 2013 || Intel [[Haswell (microarchitecture)|Haswell]] || || [[Advanced Vector Extensions 2|AVX2]], [[FMA instruction set|FMA3]], [[Transactional Synchronization Extensions|TSX]], [[Bit Manipulation Instruction Sets|BMI1, and BMI2]] instructions.
|-
| &mdash;<br>([[Many Integrated Core|MIC]] pilot) <!-- 5/8/10 --> || 2012 || Intel [[Xeon Phi]] ([[Larrabee (microarchitecture)|Larrabee]]) || || Many Integrated Cores (62), In-order [[P5 (microarchitecture)|P54C]] with x86-64, Very wide [[vector processing|vector unit]], LRBni instructions (8× 64-bit)
<!--
|-
| 10 ([[System on a chip|SoC]], [[Many Integrated Core|MIC]]) || 2015/2016 || Intel [[Skylake (microarchitecture)|Skylake]]/[[Skymont (microarchitecture)|Skymont]] || || [[Out-of-order execution|Out-of-order]], 64-bit (integer CPU), AVX3, integrated on-die [[Southbridge (computing)|southbridge]], integrated on-die x86 MIC array [[Graphics processing unit|GPU]] -->
|}
 
==History==
 
===Background===
The x86 architecture was first used for the [[Intel 8086]] Central Processing Unit ([[Central processing unit|CPU]]) released during 1978, a fully 16-bit design based on the earlier 8-bit based [[Intel 8008|8008]] and [[Intel 8080|8080]]. Although not binary compatible, it was designed to allow [[assembly language]] programs written for these processors (as well as the contemporary [[8085]]) to be mechanically translated into equivalent [[x86 assembly language|8086 assembly]]. This made the new processor a tempting software migration route for many customers. However, the 16-bit external databus of the 8086 implied fairly significant hardware redesign, as well as other complications and expenses. To address this obstacle, Intel introduced the almost identical [[Intel 8088|8088]], basically an 8086 with an 8-bit external databus that permitted simpler [[printed circuit board]]s and demanded fewer (1-bit wide) [[DRAM]] chips; it was also more easily interfaced to already established (i.e. low-cost) 8-bit system and peripheral chips. Among other, non-technical factors, this contributed to IBM's decision to design a [[home computer]] / [[personal computer]] based on the 8088, despite a presence of 16-bit microprocessors from Motorola, Zilog, and National Semiconductor (as well as several established 8-bit processors, which were also considered). The resulting [[IBM PC]] subsequently became preferred to [[Z80]]-based [[CP/M]] systems, [[Apple II]]s, and other popular computers as the [[de facto standard]] for personal computers, thus enabling the 8088 and its successors to dominate this large part of the microprocessor market.
 
====iAPX 432 and the 80286====
Another factor was that the advanced but non-compatible 32-bit [[IAPX 432|Intel 8800]] (alias iAPX 432) failed in the market around the time the original IBM-PC was initiated; the new and fast [[Intel 80286|80286]] actually contributed to the disappointment in the performance of the semi-contemporary 8800 during early 1982. (The [[Intel 80186|80186]], initiated simultaneously with the 80286, was intended for [[embedded systems]], and would therefore have had a large market anyway.) The market failure of the 32-bit 8800 was a significant impetus for Intel to continue to develop more advanced 8086-compatible processors instead, such as the [[Intel 80386|80386]] (a 32-bit extension of the well performing 80286).
 
===Other manufacturers===
[[Image:Am386SXL-25cropped.jpg|thumb|120px|[[Am386]] released by AMD in 1991.]]
{{further2|[[List of former IA-32 compatible processor manufacturers]]}}
 
At various times, companies such as [[IBM]], [[NEC]],{{Efn|The NEC V20 and V30 also provided the older 8080 instruction set, allowing PCs equipped with these microprocessors to operate CP/M applications at full speed (i.e. without the need to simulate a 8080 by software).}} [[AMD]], [[Texas Instruments|TI]], [[STMicroelectronics|STM]], [[Fujitsu]], [[Oki Electric Industry|OKI]], [[Siemens AG|Siemens]], [[Cyrix]], [[Intersil]], [[Chips and Technologies|C&T]], [[NexGen]], [[United Microelectronics Corporation|UMC]], and [[DM&P]] started to design and/or manufacture x86 [[central processing unit|processors]] (CPUs) intended for personal computers as well as embedded systems. Such x86 implementations are seldom simple copies but often employ different internal [[microarchitecture]]s as well as different solutions at the electronic and physical levels. Quite naturally, early compatible microprocessors were 16-bit, while 32-bit designs were developed much later. For the [[personal computer]] market, real quantities started to appear around 1990 with [[i386]] and [[i486]] compatible processors, often named similarly to Intel's original chips. Other companies, which designed or manufactured x86 or [[x87]] processors, include [[ITT Corporation]], [[National Semiconductor]], [[ULSI System Technology]], and [[Weitek]].
 
Following the fully [[pipelining|pipelined]] [[i486]], [[Intel Corporation|Intel]] introduced the [[Pentium (brand)|Pentium]] brand name (which, unlike numbers, could be trademarked) for their new set of [[superscalar]] x86 designs. With the x86 naming scheme now legally cleared, [[IBM]] partnered with [[Cyrix]] to produce the [[Cyrix Cx5x86|5x86]] and then the very efficient [[6x86]] (M1) and [[6x86]]MX ([[Cyrix 6x86|MII]]) lines of Cyrix designs, which were the first x86 microprocessors implementing [[register renaming]] to enable [[speculative execution]]. AMD meanwhile designed and manufactured the advanced but delayed [[5k86]] ([[AMD K5|K5]]), which, ''internally'', was closely based on AMD's earlier [[29K]] [[RISC]] design; similar to [[NexGen]]'s [[Nx586]], it used a strategy such that dedicated pipeline stages decode x86 instructions into uniform and easily handled [[micro-operation]]s, a method that has remained the basis for most x86 designs to this day.
 
Some early versions of these microprocessors had heat dissipation problems. The 6x86 was also affected by a few minor compatibility problems, the [[Nx586]] lacked a [[floating point unit]] (FPU) and (the then crucial) pin-compatibility, while the [[AMD K5|K5]] had somewhat disappointing performance when it was (eventually) introduced. Customer ignorance of alternatives to the Pentium series further contributed to these designs being comparatively unsuccessful, despite the fact that the [[AMD K5|K5]] had very good Pentium compatibility and the [[6x86]] was significantly faster than the Pentium on integer code.{{Efn|It had a slower FPU however, which is slightly ironic as Cyrix started out as a designer of fast Floating point units for x86 processors.}} [[AMD]] later managed to establish itself as a serious contender with the [[AMD K6|K6]] set of processors, which gave way to the very successful [[Athlon]] and [[Opteron]]. There were also other contenders, such as [[Centaur Technology]] (formerly [[Integrated Device Technology|IDT]]), [[Rise Technology]], and [[Transmeta]]. [[VIA Technologies]]' energy efficient [[VIA C3|C3]] and [[VIA C7|C7]] processors, which were designed by [[Centaur Technology|Centaur]] company, have been sold for many years. Centaur's newest design, the [[VIA Nano]], is their first processor with [[superscalar]] and [[speculative execution]]. It was, perhaps interestingly, introduced at about the same time as Intel's first "in-order" processor since the [[P5 (microarchitecture)|P5]] [[Pentium (brand)|Pentium]], the [[Intel Atom]].
 
===Extensions of word size===
The [[instruction set architecture]] has twice been extended to a larger [[Word (data type)|word size]]. In 1985, Intel released the 32-bit 80386 (later known as i386) which gradually replaced the earlier 16-bit chips in computers (although typically not in [[embedded system]]s) during the following years; this extended programming model was originally referred to as ''the i386 architecture'' (like its first implementation) but Intel later dubbed it [[IA-32]] when introducing its (unrelated) [[IA-64]] architecture. In 1999-2003, [[Advanced Micro Devices|AMD]] extended this 32-bit architecture to 64&nbsp;bits and referred to it as [[x86-64]] in early documents and later as [[AMD64]]. Intel soon adopted AMD's architectural extensions under the name IA-32e, later using the name EM64T and finally using Intel 64. Among these five names, the original x86-64 is probably the most commonly used, although [[Microsoft]] and [[Sun Microsystems]] also use the term x64.
 
==Overview==
 
===Basic properties of the architecture===
The x86 architecture is a variable instruction length, primarily "[[Complex instruction set computer|CISC]]" design with emphasis on [[backward compatibility]]. The instruction set is not typical CISC, however, but basically an extended version of the simple eight-bit [[Intel 8008|8008]] and [[Intel 8080|8080]] architectures. Byte-addressing is enabled and words are stored in memory with [[endianness|little-endian]] byte order. Memory access to unaligned addresses is allowed for all valid word sizes. The largest native size for [[integer (computing)|integer]] ''arithmetic'' and memory addresses (or [[offset (computer science)|offset]]s) is 16, 32 or 64&nbsp;bits depending on architecture generation (newer processors include direct support for smaller integers as well). Multiple scalar values can be handled simultaneously via the SIMD unit present in later generations, as described below.{{Efn|16-bit and 32-bit microprocessors were introduced during 1978 and 1985 respectively; plans for 64-bit was announced during 1999 and gradually introduced from 2003 and onwards.}} Immediate addressing offsets and immediate data may be expressed as 8-bit quantities for the frequently occurring cases or contexts where a -128..127 range is enough. Typical instructions are therefore 2 or 3 bytes in length (although some are much longer, and some are single-byte).
 
To further conserve encoding space, most registers are expressed in opcodes using three bits, and at most one operand to an instruction can be a memory location (some "CISC" designs, such as the [[PDP-11]], may use two). However, this memory operand may also be the ''destination'' (or a combined ''source'' '''and''' ''destination''), while the other operand, the ''source'', can be either ''register'' or ''immediate''. Among other factors, this contributes to a code size that rivals eight-bit machines and enables efficient use of instruction cache memory. The relatively small number of general registers (also inherited from its 8-bit ancestors) has made register-relative addressing (using small immediate offsets) an important method of accessing operands, especially on the stack. Much work has therefore been invested in making such accesses as fast as register accesses, i.e. a one cycle instruction throughput, in most circumstances where the accessed data is available in the top-level cache.
 
====Floating point and SIMD====
A dedicated [[floating point processor]] with 80-bit internal registers, the [[Intel 8087|8087]], was developed for the original [[8086]]. This microprocessor subsequently developed into the extended [[80387]], and later processors incorporated a [[backward compatible]] version of this functionality on the same microprocessor as the main processor. In addition to this, modern x86 designs also contain a [[SIMD]]-unit (see [[Streaming SIMD Extensions|SSE]] below) where instructions can work in parallel on (one or two) 128-bit words, each containing 2 or 4 [[floating point number]]s (each 64 or 32&nbsp;bits wide respectively), or alternatively, 2, 4, 8 or 16 integers (each 64, 32, 16 or 8&nbsp;bits wide respectively).
 
The presence of wide SIMD registers means that existing x86 processors can load or store up to 128&nbsp;bits of memory data in a single instruction and also perform bitwise operations (although not integer arithmetic{{Efn|That is because integer arithmetic generates carry between subsequent bits (unlike simple bitwise operations).}}) on full 128-bits quantities in parallel. Intel's [[Sandy Bridge]] processors added the AVX (Advanced Vector Extensions) instructions. widening the SIMD registers to 256 bits. Knights Corner, the architecture used by Intel on their Xeon Phi co-processors, uses 512-bit wide SIMD registers.
<!-- The fact that "MOV" has been extended to cope with 128-bit words does not make the 128-bit SSE registers general purpose. The bitwise instructions extended for 128-bit SSE registers and memory locations is just SSE/SIMD, plain and simple. The fact that 128-bit registers can be pushed and popped to/from the stack with "normal instructions" is nothing more remarkable than the "MOV" mentioned above (although very useful). Only 128-bit SSE words (not 128-bit integers or addresses) are enabled by the single-instruction-single-data core. What opcodes are used are irrelevant here.-->
 
===Current implementations===
{{unreferenced section|date=February 2013}}
During [[Execution (computers)|execution]], current x86 processors employ a few extra decoding steps to split most instructions into smaller pieces (micro-operations). These are then handed to a [[control unit]] that buffers and schedules them in compliance with x86-semantics so that they can be executed, partly in parallel, by one of several (more or less specialized) [[execution units]]. These modern x86 designs are thus [[superscalar]], and also capable of [[out of order execution|out of order]] and [[speculative execution]] (via [[register renaming]]), which means they may execute multiple (partial or complete) x86 instructions simultaneously, and not necessarily in the same order as given in the instruction stream.
 
When introduced, in the mid-1990s, this method was sometimes referred to as a "RISC core" or as "RISC translation", partly for marketing reasons, but also because these micro-operations share some properties with certain types of RISC instructions. However, ''traditional'' [[microcode]] (used since the 1950s) also inherently shares many of the same properties; the new method differs mainly in that the translation to micro-operations now occurs asynchronously. Not having to synchronize the execution units with the decode steps opens up possibilities for more analysis of the (buffered) code stream, and therefore permits detection of operations that can be performed in parallel, simultaneously feeding more than one execution unit.
 
The latest processors also do the opposite when appropriate; they combine certain x86 sequences (such as a compare followed by a conditional jump) into a more complex micro-op which fits the execution model better and thus can be executed faster or with less machine resources involved.
 
Another way to try to improve performance is to cache the decoded micro-operations, so the processor can directly access the decoded micro-operations from a special cache, instead of decoding them again. Intel followed this approach with the Execution Trace Cache feature in their NetBurst Microarchitecture (for Pentium 4 processors) and later in the Decoded Stream Buffer (for Core-branded processors since Sandy Bridge).<ref>{{cite web|url=http://software.intel.com/sites/products/documentation/doclib/iss/2013/amplifier/lin/ug_docs/GUID-143D1B76-D97F-454F-9B4B-91F2D791B66D.htm|title=DSB Switches|work=Intel VTune Amplifier 2013|publisher=Intel|accessdate=August 26, 2013}}</ref>
 
[[Transmeta]] used a completely different method in their x86 compatible CPUs. They used [[Just-in-time compilation|just-in-time]] translation to convert x86 instructions to the CPU's native [[VLIW]] instruction set. Transmeta argued that their approach allows for more power efficient designs since the CPU can forgo the complicated decode step of more traditional x86 implementations.
 
==Segmentation==
{{unreferenced section|date=February 2013}}
{{further2|[[x86 memory segmentation]]}}
Minicomputers during the late 1970s were running up against the 16-bit 64-[[kilobyte|KB]] address limit, as memory had become cheaper. Some minicomputers like the [[PDP-11]] used complex bank-switching schemes, or, in the case of Digital's [[VAX]], redesigned much more expensive processors which could directly handle 32-bit addressing and data. The original 8086, developed from the simple [[Intel 8080|8080]] microprocessor and primarily aiming at very small and inexpensive computers and other specialized devices, instead adopted simple segment registers which increased the memory address width by only 4&nbsp;bits. By multiplying a 64-KB address by 16, the 20-bit address could address a total of one [[megabyte]] (1,048,576 bytes) which was quite a large amount for a small computer at the time.  The concept of segment registers was not new to many mainframes which used segment registers to swap quickly to different tasks. In practice, on the x86 it was (is) a much-criticized implementation which greatly complicated many common programming tasks and compilers. However, the architecture soon allowed [[Linear addressing|linear]] 32-bit addressing (starting with the 80386 in late 1985) but major actors (such as [[Microsoft]]) took several years to convert their 16-bit based systems. The 80386 (and 80486) was therefore largely used as a fast (but still 16-bit based) 8086 for many years.
 
Data and/or code could be managed within "near" 16-bit segments within 64kB portions of the total 1[[megabyte|MB]] address space, or a compiler could operate in a "far" mode using 32-bit <code>segment:offset</code> pairs reaching (only) 1&nbsp;MB. This would prove to be quite limiting by the mid-1980s, and during 1985, the 16-bit segment addressing model was effectively factored out by the introduction of 32-bit offset registers, in the [[Intel 80386|386]] design.
 
In [[real mode]], segmentation is achieved by [[Bit shift|shifting]] the segment address left by 4&nbsp;bits and adding an offset in order to receive a final 20-bit address. For example, if DS is A000h and SI is 5677h, DS:SI will point at the absolute address DS &times; 10h + SI = A5677h. Thus the total address space in real mode is 2<sup>20</sup> bytes, or 1 [[megabyte|MB]], quite an impressive figure for 1978. All memory addresses consist of both a segment and offset; every type of access (code, data, or stack) has a default segment register associated with it (for data the register is usually DS, for code it is CS, and for stack it is SS). For data accesses, the segment register can be explicitly specified (using a segment override prefix) to use any of the four segment registers.
 
In this scheme, two different segment/offset pairs can point at a single absolute location. Thus, if DS is A111h and SI is 4567h, DS:SI will point at the same A5677h as above. This scheme makes it impossible to use more than four segments at once. CS and SS are vital for the correct functioning of the program, so that only DS and ES can be used to point to data segments outside the program (or, more precisely, outside the currently executing segment of the program) or the stack.
 
In [[protected mode]], a segment register no longer contains the physical address of the beginning of a segment, but contain a "selector" that points to a system-level structure called a ''segment descriptor''. A segment descriptor contains the physical address of the beginning of the segment, the length of the segment, and access permissions to that segment. The offset is checked against the length of the segment, with offsets referring to locations outside the segment causing an exception. Offsets referring to locations inside the segment are combined with the physical address of the beginning of the segment to get the physical address corresponding to that offset.
 
The segmented nature can make programming and compiler design difficult because the use of near and far pointers affects performance.
 
==Addressing modes==
{{unreferenced section|date=February 2013}}
[[Addressing mode]]s for 16-bit x86 processors can be summarized by this formula:
 
:<math>
\begin{Bmatrix}CS:\\DS:\\SS:\\ES:\end{Bmatrix}
\begin{bmatrix}\begin{Bmatrix}BX\\BP\end{Bmatrix}\end{bmatrix} +
\begin{bmatrix}\begin{Bmatrix}SI\\DI\end{Bmatrix}\end{bmatrix} +
\rm [displacement]
</math>
 
Addressing modes for 32-bit address size on 32-bit or 64-bit x86 processors can be summarized by this formula:
 
:<math>
\begin{Bmatrix}CS:\\DS:\\SS:\\ES:\\FS:\\GS:\end{Bmatrix}
\begin{bmatrix}\begin{Bmatrix}EAX\\EBX\\ECX\\EDX\\ESP\\EBP\\ESI\\EDI\end{Bmatrix}\end{bmatrix} +
\begin{bmatrix}\begin{Bmatrix}EAX\\EBX\\ECX\\EDX\\EBP\\ESI\\EDI\end{Bmatrix}*\begin{Bmatrix}1\\2\\4\\8\end{Bmatrix}\end{bmatrix} +
\rm [displacement]
</math>
 
Addressing modes for 64-bit code on 64-bit x86 processors can be summarized by this formula:
 
:<math>
\begin{Bmatrix}
\begin{Bmatrix}FS:\\GS:\end{Bmatrix}
\begin{bmatrix}{\rm general\;register}\end{bmatrix} +
\begin{bmatrix}{\rm general\;register}*\begin{Bmatrix}1\\2\\4\\8\end{Bmatrix}\end{bmatrix}\\\\
RIP
\end{Bmatrix} +
\rm [displacement]
</math>
 
Instruction relative addressing in 64-bit code (RIP + displacement, where RIP is the instruction pointer register) simplifies the implementation of [[position-independent code]] (as used in [[shared libraries]] in some operating systems).
 
The 8086 had 64&nbsp;KB of 8-bit (or alternatively 32&nbsp;K-word of 16-bit) [[I/O]] space, and a 64&nbsp;KB (one segment) [[Stack (data structure)|stack]] in memory supported by [[computer hardware]]. Only words (2&nbsp;bytes) can be pushed to the stack. The stack grows downwards (toward numerically lower addresses), its bottom being pointed by SS:SP. There are 256 [[interrupt]]s, which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the [[Return statement|return address]].
 
==x86 registers==
''For a description of the general notion of a CPU register, see [[Processor register]].''
 
===16-bit===
The original [[Intel 8086]] and [[Intel 8088|8088]] have fourteen 16-[[bit]] registers. Four of them (AX, BX, CX, DX) are general-purpose registers (GPRs), although each may have an additional purpose; for example, only CX can be used as a counter with the ''loop'' instruction. Each can be accessed as two separate bytes (thus BX's high byte can be accessed as BH and low byte as BL). Two pointer registers have special roles: SP points to the ‘top’ of the [[stack]] and BP (base pointer) is often used to point at some other place in the stack, typically above the local variables (see [[frame pointer]]). The registers SI, DI, BX and BP are [[address register]]s, and may also be used for array indexing.
 
Four segment registers (CS, DS, SS and ES) are used to form a memory address. The [[FLAGS register (computing)|FLAGS register]] contains [[Flag (computing)|flag]]s such as [[carry flag]], [[overflow flag]] and [[zero flag]]. Finally, the instruction pointer (IP) points to the next instruction that will be fetched from memory and then executed.
 
The [[Intel 80186]] and [[Intel 80188|80188]] are essentially an upgraded 8086 or 8088 CPU, respectively, with on-chip peripherals added, and they have the same CPU registers as the 8086 and 8088 (in addition to interface registers for the peripherals).
 
The 8086, 8088, 80186, and 80188 can use an optional floating-point coprocessor, the [[Intel 8087|8087]].  The 8087 appears to the programmer as part of the CPU and adds eight 80-bit wide registers, st(0) to st(7), each of which can hold numeric data in one of seven formats: 32-, 64-, or 80-bit floating point, 16-, 32-, or 64-bit (binary) integer, and 80-bit packed decimal integer.<ref>Intel iAPX 86,88 User's Manual, August 1981, p. S-6, S-13..S-15 (Order No. 210201-001)</ref>
 
In the [[Intel 80286]], to support [[Protected Mode]], three special registers hold descriptor table addresses (GDTR, LDTR, [[Interrupt descriptor table|IDTR]]), and a fourth task register (TR) is used for task switching.  The [[Intel 80287|80287]] is the floating-point coprocessor for the 80286 and has the same registers as the 8087 with the same data formats.
 
===32-bit===
With the advent of the 32-bit [[Intel 80386|80386]] processor, the 16-bit general-purpose registers, base registers, index registers, instruction pointer, and [[FLAGS register]], but not the segment registers, were expanded to 32&nbsp;bits. This is represented by prefixing an "'''E'''" (for '''Extended''') to the register names in [[x86 assembly language]]. Thus, the AX register corresponds to the lowest 16&nbsp;bits of the new 32-bit EAX register, SI corresponds to the lowest 16&nbsp;bits of ESI, and so on. The general-purpose registers, base registers, and index registers can all be used as the base in addressing modes, and all of those registers except for the stack pointer can be used as the index in addressing modes.
 
Two new segment registers (FS and GS) were added. With a greater number of registers, instructions and operands, the [[machine code]] format was expanded. To provide backward compatibility, segments with executable code can be marked as containing either 16-bit or 32-bit instructions. Special prefixes allow inclusion of 32-bit instructions in a 16-bit segment or vice versa.
 
[[File:Table of x86 Registers.png|thumb|The registers available in the x86 instruction set.]]
 
The 80386 had an optional floating-point coprocessor, the [[80387]]; it had eight 80-bit wide registers: st(0) to st(7),<ref>{{cite book|url=http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-1-manual.pdf|title=Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 1: Basic Architecture|at=Chapter 8|publisher=Intel|date=March 2013}}</ref> like the 8087 and 80287. (The 80386 could also use an 80287 coprocessor.) With the [[80486]] and all subsequent x86 models, the floating-point processing unit (FPU) was integrated on-chip.
 
With the [[Pentium MMX]], eight 64-bit MMX integer registers were added (MMX0 to MMX7, which share lower bits with the 80-bit-wide FPU stack).<ref>{{cite book|url=http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-1-manual.pdf|title=Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 1: Basic Architecture|at=Chapter 9|publisher=Intel|date=March 2013}}</ref> With the [[Pentium III]], a 32-bit [[Streaming SIMD Extensions]] (SSE) control/status register (MXCSR) and eight 128-bit SSE floating point registers (XMM0 to XMM7) were added.<ref>{{cite book|url=http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-1-manual.pdf|title=Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 1: Basic Architecture|at=Chapter 10|publisher=Intel|date=March 2013}}</ref>
 
===64-bit===
Starting with the [[AMD Opteron]] processor, the x86 architecture extended the 32-bit registers into 64-bit registers in a way similar to how the 16 to 32-bit extension took place. An '''R'''-prefix identifies the 64-bit registers (RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP, RFLAGS, RIP), and eight additional 64-bit general registers (R8-R15) were also introduced in the creation of [[x86-64]]. However, these extensions are only usable in 64-bit mode, which is one of the two modes only available in [[long mode]]. The addressing modes were not dramatically changed from 32-bit mode, except that addressing was extended to 64&nbsp;bits, virtual addresses are now sign extended to 64&nbsp;bits (in order to disallow mode bits in virtual addresses), and other selector details were dramatically reduced. In addition, an addressing mode was added to allow memory references relative to RIP (the [[instruction pointer]]), to ease the implementation of [[position-independent code]], used in shared libraries in some operating systems.
 
===128-bit===
{{see also|Streaming SIMD Extensions#Registers}}
SIMD registers XMM0–XMM15.
 
===256-bit===
{{see also|Advanced Vector Extensions#New features}}
SIMD registers YMM0–YMM15.
 
===512-bit===
{{see also|Advanced Vector Extensions#AVX-512}}
SIMD registers ZMM0–ZMM31.
 
===Miscellaneous/special purpose===
x86 processors that have a [[Protected Mode]], i.e. the 80286 and later processors, also have three descriptor registers (GDTR, LDTR, [[Interrupt descriptor table|IDTR]]) and a task register (TR).
 
32-bit x86 processors (starting with the 80386) also include various special/miscellaneous registers such as [[control register]]s (CR0 through 4, CR8 for 64-bit only), [[debug register]]s (DR0 through 3, plus 6 and 7), [[test register]]s (TR3 through 7; 80486 only), and model-specific registers (MSRs, appearing with the Pentium{{Efn|Two MSRs of particular interest are SYSENTER_EIP_MSR<!-- (0x176) --> and SYSENTER_ESP_MSR<!-- (0x175) -->, introduced on the Pentium® II processor, which store the address of the kernel mode system service handler<!-- nt!KiFastCallEntry --> and corresponding kernel stack pointer. Initialized during system startup, SYSENTER_EIP_MSR and SYSENTER_ESP_MSR are used by the SYSENTER (Intel) or SYSCALL (AMD) instructions to achieve Fast System Calls, about three times faster<!-- http://www.codeguru.com/cpp/misc/misc/system/article.php/c8223/System-Call-Optimization-with-the-SYSENTER-Instruction.htm 266% as fast (166% faster) on a PIII Dual 800 MHz --> than the software interrupt method used previously.}}).
 
===Purpose===
Although the main registers (with the exception of the instruction pointer) are "general-purpose" in the 32-bit and 64-bit versions of the instruction set and can be used for anything, it was originally envisioned that they be used for the following purposes:
* AL/AH/AX/EAX/RAX: Accumulator
* BL/BH/BX/EBX/RBX: Base index (for use with arrays)
* CL/CH/CX/ECX/RCX: Counter (for use with loops and strings)
* DL/DH/DX/EDX/RDX: Extend the precision of the accumulator (e.g. combine 32-bit EAX and EDX for 64-bit integer operations in 32-bit code)
* SI/ESI/RSI: ''Source index'' for [[string (computer science)|string]] operations.
* DI/EDI/RDI: ''Destination index'' for string operations.
* SP/ESP/RSP: Stack pointer for top address of the stack.
* BP/EBP/RBP: Stack base pointer for holding the address of the current [[stack frame]].
* IP/EIP/RIP: Instruction pointer. Holds the [[program counter]], the current instruction address.
 
Segment registers:
*CS: Code
*DS: Data
*SS: Stack
*ES: Extra data
*FS: Extra data #2
*GS: Extra data #3
 
No particular purposes were envisioned for the other 8 registers available only in 64-bit mode.
 
Some instructions compile and execute more efficiently when using these registers for their designed purpose. For example, using AL as an [[Accumulator (computing)|accumulator]] and adding an immediate byte value to it produces the efficient ''add to AL'' [[opcode]] of 04h, whilst using the BL register produces the generic and longer ''add to register'' opcode of 80C3h. Another example is double precision division and multiplication that works specifically with the AX and DX registers.
 
Modern compilers benefited from the introduction of the ''sib'' byte (''scale-index-base byte'') that allows registers to be treated uniformly ([[minicomputer]]-like).  However, using the sib byte universally is inoptimal, as it produces longer encodings than only using it selectively when necessary.  (The main benefit of the sib byte is the orthogonality and more powerful addressing modes it provides, which make it possible to save instructions and the use of registers for address calculations such as scaling an index.)  Some special instructions lost priority in the hardware design and became slower than equivalent small code sequences. A notable example is the LODSW instruction.
 
===Structure===
{| class="wikitable"
|+ General Purpose Registers (A, B, C and D)
! style="width:50pt;"| 64
! style="width:50pt;"| 56
! style="width:50pt;"| 48
! style="width:50pt;"| 40
! style="width:50pt;"| 32
! style="width:50pt;"| 24
! style="width:50pt;"| 16
! style="width:50pt;"| 8
|-
| colspan="8" style="text-align:center;"| R?X
|-
| colspan="4" style="background:lightgrey" |
| colspan="4" style="text-align:center;"| E?X
|-
| colspan="6" style="background:lightgrey" |
| colspan="2" style="text-align:center;"| ?X
|-
| colspan="6" style="background:lightgrey" |
| style="text-align:center;"| ?H
| style="text-align:center;"| ?L
|}
 
{| class="wikitable"
|+ 64-bit mode-only General Purpose Registers (R8, R9, R10, R11, R12, R13, R14, R15)
! style="width:50pt;"| 64
! style="width:50pt;"| 56
! style="width:50pt;"| 48
! style="width:50pt;"| 40
! style="width:50pt;"| 32
! style="width:50pt;"| 24
! style="width:50pt;"| 16
! style="width:50pt;"| 8
|-
| colspan="8" style="text-align:center;"| ?
|-
| colspan="4" style="background:lightgrey" |
| colspan="4" style="text-align:center;"| ?D
|-
| colspan="6" style="background:lightgrey" |
| colspan="2" style="text-align:center;"| ?W
|-
| colspan="7" style="background:lightgrey" |
| style="text-align:center;"| ?B
|}
 
{| class="wikitable"
|+ Segment Registers (C, D, S, E, F and G)
! style="width:50pt;"| 16
! style="width:50pt;"| 8
|-
| colspan="2" style="text-align:center;"| ?S
|}
 
{| class="wikitable"
|+ Pointer Registers (S and B)
! style="width:50pt;"| 64
! style="width:50pt;"| 56
! style="width:50pt;"| 48
! style="width:50pt;"| 40
! style="width:50pt;"| 32
! style="width:50pt;"| 24
! style="width:50pt;"| 16
! style="width:50pt;"| 8
|-
| colspan="8" style="text-align:center;"| R?P
|-
| colspan="4" style="background:lightgrey" |
| colspan="4" style="text-align:center;"|E?P
|-
| colspan="6" style="background:lightgrey" |
| colspan="2" style="text-align:center;"|?P
|-
| colspan="7" style="background:lightgrey" |
| style="text-align:center;"| ?PL
|}
Note: The ?PL registers are only available in 64-bit mode.
 
{| class="wikitable"
|+ Index Registers (S and D)
! style="width:50pt;"| 64
! style="width:50pt;"| 56
! style="width:50pt;"| 48
! style="width:50pt;"| 40
! style="width:50pt;"| 32
! style="width:50pt;"| 24
! style="width:50pt;"| 16
! style="width:50pt;"| 8
|-
| colspan="8" style="text-align:center;"| R?I
|-
| colspan="4" style="background:lightgrey" |
| colspan="4" style="text-align:center;"| E?I
|-
| colspan="6" style="background:lightgrey" |
| colspan="2" style="text-align:center;"| ?I
|-
| colspan="7" style="background:lightgrey" |
| style="text-align:center;"| ?IL
|}
Note: The ?IL registers are only available in 64-bit mode.
 
{| class="wikitable"
|+ Instruction Pointer Register (I)
! style="width:50pt;"| 64
! style="width:50pt;"| 56
! style="width:50pt;"| 48
! style="width:50pt;"| 40
! style="width:50pt;"| 32
! style="width:50pt;"| 24
! style="width:50pt;"| 16
! style="width:50pt;"| 8
|-
| colspan="8" style="text-align:center;"| RIP
|-
| colspan="4" style="background:lightgrey" |
| colspan="4" style="text-align:center;"| EIP
|-
| colspan="6" style="background:lightgrey" |
| colspan="2" style="text-align:center;"| IP
|}
 
==Operating modes==
 
===Real mode===
{{refimprove section|date=January 2014}}
{{main|Real mode}}
 
Real Address mode,<ref>{{cite web|url=http://bitsavers.org/pdf/intel/80286/210498-001_1983_iAPX_286_Programmers_Reference_1983.pdf|title=iAPX 286 Programmer's Reference|at=Section 1.2, "Modes of Operation"|publisher=Intel|year=1983|accessdate=January 27, 2014}}</ref> commonly called Real mode, is an operating mode of [[8086]] and later x86-compatible [[Central processing unit|CPUs]]. Real mode is characterized by a 20-bit segmented memory address space (meaning that only 1 [[Mebibyte|MiB]] of memory can be addressed&mdash;actually, slightly more{{Efn|Because a segmented address is the sum of a 16-bit segment multiplied by 16 and a 16-bit offset, the maximum address is 1,114,095 (10FFEF&nbsp;hex), for an addressability of 1,114,096&nbsp;bytes&nbsp;{{=}} 1&nbsp;MiB&nbsp;+ 65,520&nbsp;bytes.  Before the 80286, x86 CPUs had only 20 physical address lines (address bit signals), so the 21st bit of the address, bit 20, was dropped and addresses past 1&nbsp;MiB were mirrors of the low end of the address space (starting from address zero). Since the 80286, all x86 CPUs have at least 24 physical address lines, and bit 20 of the computed address is brought out onto the address bus in real mode, allowing the CPU to address the full 1,114,096 bytes reachable with an x86 segmented address. On the popular IBM PC platform, switchable hardware to disable the 21st address bit was added to machines with an 80286 or later so that all programs designed for 8088/8086-based models could run, while newer software could take advantage of the "high" memory in real mode and the full 16&nbsp;MiB or larger address space in protected mode&mdash;see A20 gate.}}), direct software access to peripheral hardware, and no concept of [[memory protection]] or [[computer multitasking|multitasking]] at the hardware level. All x86 CPUs in the [[Intel 80286|80286]] series and later start up in real mode at power-on; [[Intel 80186|80186]] CPUs and earlier had only one operational mode, which is equivalent to real mode in later chips.  (On the IBM PC platform, direct software access to the IBM [[BIOS]] routines is available only in real mode, since BIOS is written for real mode.  However, this is not a characteristic of the x86 CPU but of the IBM BIOS design.)
 
In order to use more than 64&nbsp;KiB of memory, the segment registers must be used. This created great complications for compiler implementors who introduced odd pointer modes such as "near", "far" and "huge" to leverage the implicit nature of segmented architecture to different degrees, with some pointers containing 16-bit offsets within implied segments and other pointers containing segment addresses and offsets within segments.  It is technically possible to use up to 256&nbsp;KiB of memory for code and data, with up to 64&nbsp;KiB for code, by setting all four segment registers once and then only using 16-bit offsets (optionally with default-segment override prefixes) to address memory, but this puts substantial
restrictions on the way data can be addressed and memory operands can be combined, and it violates the architectural intent of the Intel designers, which is for separate data items (e.g. arrays, structures, code units) to be contained in separate segments and addressed by their own segment addresses, in new programs that are not ported from earlier 8-bit processors with 16-bit address spaces.
 
===Protected mode===
{{refimprove section|date=January 2014}}
{{main|Protected mode}}
 
In addition to real mode, the Intel 80286 supports protected mode, expanding addressable [[physical memory]] to 16 [[megabyte|MB]] and addressable [[virtual memory]] to 1&nbsp;[[gigabyte|GB]], and providing [[protected memory]], which prevents programs from corrupting one another. This is done by using the segment registers only for storing an index into a descriptor table that is stored in memory.  There are two such tables, the [[Global Descriptor Table]]  (GDT) and the [[Local Descriptor Table]] (LDT), each holding up to 8192 segment descriptors, each segment giving access to 64&nbsp;KB of memory. In the 80286, a segment descriptor provides a 24-bit [[base address]], and this base address is added to a 16-bit offset to create an absolute address.  The base address from the table fulfills the same role that the literal value of the segment register fulfills in real mode; the segment registers have been converted from direct registers to indirect registers.  Each segment can be assigned one of four [[ring (computer security)|ring]] levels used for hardware-based [[computer security]].  Each segment descriptor also contains a segment limit field which specifies the maximum offset that may be used with the segment.  Because offsets are 16 bits, segments are still limited to 64&nbsp;KiB each in 80286 protected mode.<ref>{{cite web|url=http://bitsavers.org/pdf/intel/80286/210498-001_1983_iAPX_286_Programmers_Reference_1983.pdf|title=iAPX 286 Programmer's Reference|at=Chapter 6, "Memory Management and Virtual Addressing"|publisher=Intel|year=1983|accessdate=January 27, 2014}}</ref>
 
Each time a segment register is loaded in protected mode, the 80286 must read a 6-byte segment descriptor from memory into an a set of hidden internal registers.  Therefore, loading segment registers is much slower in protected mode than in real mode, and changing segments very frequently is to be avoided.  Actual memory operations using protected mode segments are not slowed much because the 80286 and later have hardware to check the offset against the segment limit in parallel with instruction execution.
 
The [[Intel 80386]] extended offsets and also the segment limit field in each segment descriptor to 32 bits, enabling a segment to span the entire memory space.  It also introduced support in protected mode for [[paging]], a mechanism making it possible to use paged [[virtual memory]] (with 4&nbsp;KiB page size).  Paging allows the CPU to map any page of the virtual memory space to any page of the physical memory space.  To do this, it uses additional mapping tables in memory called page tables.  Protected Mode on the 80386 can operate with paging either enabled or disabled; the segmentation mechanism is always active and generates virtual addresses that are then mapped by the paging mechanism if it is enabled.  The segmentation mechanism can also be effectively disabled by setting all segments to have a base address of 0 and size limit equal to the whole address space; this also requires a minimally-sized segment descriptor table of only four descriptors (since the FS and GS segments need not be used).{{Efn|An extra descriptor record at the top of the table is also required, because the table starts at zero but the minimum descriptor index that can be loaded into a segment register is 1; the value 0 is reserved to represent a segment register that points to no segment.}}
 
Paging is used extensively by modern multitasking operating systems. [[Linux]], [[386BSD]] and [[Windows NT]] were developed for the 386 because it was the first Intel architecture CPU to support paging and 32-bit segment offsets. The 386 architecture became the basis of all further development in the x86 series.
 
x86 processors that support protected mode boot into [[real mode]] for backward compatibility with the older 8086 class of processors. Upon power-on (a.k.a. [[booting]]), the processor initializes in real mode, and then begins executing instructions. Operating system boot code, which might be stored in [[Read-only memory|ROM]], may place the processor into the [[protected mode]] to enable paging and other features. The instruction set in protected mode is backward compatible with the one used in real mode.
 
====Virtual 8086 mode====
{{main|Virtual 8086 mode}}
 
There is also a sub-mode of operation in 32-bit protected mode (a.k.a. 80386 protected mode) called ''[[virtual 8086 mode]]'', also known as ''V86 mode''. This is basically a special hybrid operating mode that allows real mode programs and operating systems to run while under the control of a protected mode supervisor operating system. This allows for a great deal of flexibility in running both protected mode programs and real mode programs simultaneously. This mode is exclusively available for the 32-bit version of protected mode; it does not exist in the 16-bit version of protected mode, or in long mode.
 
===Long mode===
{{main|Long mode}}
 
By 2002, it was obvious that the 32-bit address space of the x86 architecture was limiting its performance in applications requiring large data sets. A 32-bit address space would allow the processor to directly address only 4&nbsp;GB of data, a size surpassed by applications such as [[Video editing software|video processing]] and [[database engine]]s. Using 64-bit addresses, one can directly address 16&nbsp;[[Exabyte|EB]] (or 16&nbsp;billion&nbsp;GB) of data, although most 64-bit architectures don't support access to the full 64-bit address space (AMD64, for example, supports only 48&nbsp;bits, split into 4 paging levels, from a 64-bit address).
 
[[AMD]] developed the [[64-bit]] extension of the 32-bit x86 architecture that is currently used in x86 processors, initially calling it ''x86-64'', later renaming it ''AMD64''. The [[Opteron]], [[Athlon 64]], [[Turion 64]], and later [[Sempron]] families of processors use this architecture. The success of the AMD64 line of processors coupled with the lukewarm reception of the IA-64 architecture forced Intel to release its own implementation of the AMD64 instruction set. Intel had previously implemented support for AMD64<ref>[http://www.geek.com/intels-yamhill-technology-x86-64-compatible/ Intel's Yamhill Technology: x86-64 compatible | Geek.com<!-- Bot generated title -->]</ref> but opted not to enable it in hopes that AMD would not bring AMD64 to market before Itanium's new IA-64 instruction set was widely adopted. It branded its implementation of AMD64 as ''EM64T'', and later re-branded it ''Intel 64''.
 
In its literature and product version names, Microsoft and Sun refer to AMD64/Intel 64 collectively as ''x64'' in the Windows and [[Solaris (operating system)|Solaris]] operating systems respectively. [[Linux distribution]]s refer to it either as "x86-64", its variant "x86_64", or "amd64". [[Berkeley Software Distribution|BSD]] systems use "amd64" while [[Mac OS X]] uses "x86_64".
 
Long mode is mostly an extension of the 32-bit instruction set, but unlike the 16–to–32-bit transition, many instructions were dropped in the 64-bit mode. This does not affect actual binary backward compatibility (which would execute legacy code in other modes that retain support for those instructions), but it changes the way assembler and compilers for new code have to work.
 
This was the first time that a ''major'' extension of the x86 architecture was initiated and originated by a manufacturer other than Intel. It was also the first time that Intel accepted technology of this nature from an outside source.
 
==Extensions==
 
===Floating point unit===
{{main|x87}}
{{further2|[[Floating point unit]]}}
Early x86 processors could be extended with [[floating-point]] hardware in the form of a series of floating point [[numerical analysis|numerical]] [[co-processor]]s with names like [[Intel 8087|8087]], 80287 and 80387, abbreviated x87. This was also known as the NPX (''Numeric Processor eXtension''), an apt name since the coprocessors, while used mainly for floating-point calculations, also performed integer operations on both binary and decimal formats.  With very few exceptions, the 80486 and subsequent x86 processors then integrated this x87 functionality on chip which made the x87 instructions a [[de facto]] integral part of the x86 instruction set.
 
Each x87 register, known as ST(0) through ST(7), is 80&nbsp;bits wide and stores numbers in the [[IEEE floating-point standard]] double extended precision format. These registers are organized as a stack with ST(0) as the top. This was done in order to conserve opcode space, and the registers are therefore randomly accessible only for either operand in a register-to-register instruction; ST0 must always be one of the two operands, either the source or the destination, regardless of whether the other operand is ST(x) or a memory operand.  However, random access to the stack registers can be obtained through an instruction which exchanges any specified ST(x) with ST(0).
 
The operations include arithmetic and transcendental functions, including trigonometric and exponential functions, as well as instructions that load common constants (such as 0; 1; e, the base of the natural logarithm; log2(10); and log10(2)) into one of the stack registers.  While the integer capability is often overlooked, the x87 can operate on larger integers with a single instruction than the 8086, 80286, 80386, or any x86 CPU without to 64-bit extensions can, and repeated integer calculations even on small values (e.g. 16-bit) can be accelerated by executing integer instructions on the x86 CPU and the x87 in parallel.  (The x86 CPU keeps running while the x87 coprocessor calculates, and the x87 sets a signal to the x86 when it is finished or interrupts the x86 if it needs attention because of an error.)
 
===MMX===
{{unreferenced section|date=February 2013}}
{{main|MMX (instruction set)}}
 
MMX is a [[SIMD]] instruction set designed by Intel, introduced in 1997 for the [[Pentium (brand)|Pentium MMX]] microprocessor. The MMX instruction set was developed from a similar concept first used on the [[Intel i860]]. It is supported on most subsequent IA-32 processors by Intel and other vendors. MMX is typically used for video processing (in "multimedia" applications for instance).
 
MMX added 8 new "registers" to the architecture, known as MM0 through MM7 (henceforth referred to as ''MMn''). In reality, these new "registers" were just aliases for the existing x87 FPU stack registers. Hence, anything that was done to the floating point stack would also affect the MMX registers. Unlike the FP stack, these MMn registers were fixed, not relative, and therefore they were randomly accessible. The instruction set did not adopt the stack-like semantics so that existing operating systems could still correctly save and restore the register state when multitasking without modifications.
 
Each of the MMn registers are 64-bit integers. However, one of the main concepts of the MMX instruction set is the concept of ''packed data types'', which means instead of using the whole register for a single 64-bit integer ([[quadword]]), one may use it to contain two 32-bit integers ([[Integer (computer science)|doubleword]]), four 16-bit integers ([[Integer (computer science)|word]]) or eight 8-bit integers ([[Integer (computer science)|byte]]). Given that the MMX's 64-bit MMn registers are aliased to the FPU stack and each of the floating point registers are 80&nbsp;bits wide, the upper 16&nbsp;bits of the floating point registers are unused in MMX. These bits are set to all ones by any MMX instruction, which correspond to the floating point representation of [[NaN]]s or infinities.
 
===3DNow!===
{{main|3DNow!}}
{{unreferenced section|date=February 2013}}
In 1997 AMD introduced 3DNow!. The introduction of this technology coincided with the rise of [[3D computer graphics|3D]] entertainment applications and was designed to improve the CPU's [[vector processing]] performance of graphic-intensive applications. 3D video game developers and 3D graphics hardware vendors use 3DNow! to enhance their performance on AMD's [[AMD K6|K6]] and [[Athlon]] series of processors.
 
3DNow! was designed to be the natural evolution of MMX from integers to floating point. As such, it uses exactly the same register naming convention as MMX, that is MM0 through MM7. The only difference is that instead of packing integers into these registers, two [[single precision]] floating point numbers are packed into each register. The advantage of aliasing the FPU registers is that the same instruction and data structures used to save the state of the FPU registers can also be used to save 3DNow! register states. Thus no special modifications are required to be made to operating systems which would otherwise not know about them.
 
===SSE===
{{unreferenced section|date=February 2013}}
{{main|Streaming SIMD Extensions|SSE2|SSE3|SSSE3|SSE4|SSE5}}
 
In 1999, Intel introduced the Streaming SIMD Extensions (SSE) [[instruction set]], following in 2000 with SSE2. The first addition allowed offloading of basic floating-point operations from the x87 stack and the second made MMX almost obsolete and allowed the instructions to be realistically targeted by conventional compilers. Introduced in 2004 along with the [[Intel Prescott|''Prescott'']] revision of the [[Pentium 4]] processor, SSE3 added specific memory and [[Thread (computing)|thread]]-handling instructions to boost the performance of Intel's [[HyperThreading]] technology. AMD licensed the SSE3 instruction set and implemented most of the SSE3 instructions for its revision E and later Athlon 64 processors. The Athlon 64 does not support HyperThreading and lacks those SSE3 instructions used only for HyperThreading.
 
SSE discarded all legacy connections to the FPU stack. This also meant that this instruction set discarded all legacy connections to previous generations of SIMD instruction sets like MMX. But it freed the designers up, allowing them to use larger registers, not limited by the size of the FPU registers. The designers created eight 128-bit registers, named XMM0 through XMM7. (''Note'': in [[x86-64|AMD64]], the number of SSE XMM registers has been increased from 8 to 16.) However, the downside was that operating systems had to have an awareness of this new set of instructions in order to be able to save their register states. So Intel created a slightly modified version of Protected mode, called Enhanced mode which enables the usage of SSE instructions, whereas they stay disabled in regular Protected mode. An OS that is aware of SSE will activate Enhanced mode, whereas an unaware OS will only enter into traditional Protected mode.
 
SSE is a SIMD instruction set that works only on floating point values, like 3DNow!. However, unlike 3DNow! it severs all legacy connection to the FPU stack. Because it has larger registers than 3DNow!, SSE can pack twice the number of [[single precision]] floats into its registers. The original SSE was limited to only single-precision numbers, like 3DNow!. The SSE2 introduced the capability to pack [[double precision]] numbers too, which 3DNow! had no possibility of doing since a double precision number is 64-bit in size which would be the full size of a single 3DNow! MMn register. At 128&nbsp;bits, the SSE XMMn registers could pack two double precision floats into one register. Thus SSE2 is much more suitable for scientific calculations than either SSE1 or 3DNow!, which were limited to only single precision. SSE3 does not introduce any additional registers.
 
===Physical Address Extension (PAE)===
{{main|Physical Address Extension}}
[[Physical Address Extension]] or PAE was first added in the Intel [[Pentium Pro]], to allow an additional 4&nbsp;bits of physical addressing in 32-bit protected mode. The size of memory in Protected mode is usually limited to 4&nbsp;[[gigabyte|GB]]. Through tricks in the processor's page and segment memory management systems, x86 operating systems may be able to access more than 32-bits of address space, even without the switchover to the 64-bit paradigm. This mode does not change the length of segment offsets or linear addresses; those are still only 32&nbsp;bits.
 
===x64===
{{main|x86-64}}
{{see also|Itanium}}
In April 2003, AMD released the first x86 processor with 64-bit physical memory address registers capable of addressing much more than 4 [[Gigabyte|GB]] of memory using the new [[x86-64]] extension (also known as x64). Intel introduced its first x86-64 processor in July 2004.
 
x86-64 had been preceded by another architecture employing 64-bit memory addressing: Intel introduced [[Itanium]] in 2001 for the high-performance computing market. However, Itanium was incompatible with x86 and is less widely used today. x86-64 also introduced the [[NX bit]], which offers some protection against security bugs caused by [[buffer overrun]]s.
 
===Virtualization===
{{main|x86 virtualization}}
Prior to 2005 x86 architecture processors were unable to meet the [[Popek and Goldberg virtualization requirements|Popek and Goldberg requirements]] - a specification for virtualization created in 1974 by [[Gerald J. Popek]] and Robert P. Goldberg. However both commercial and open source [[x86 virtualization]] hypervisor products were developed using [[Shadow page tables|software-based virtualization]]. Commercial systems included [[VMware ESX]], VMware Workstation, [[Parallels Workstation|Parallels]], [[Microsoft]] [[Hyper-V]] Server, and [[Virtual PC|Microsoft Virtual PC]]; while open source systems included [[QEMU]]/[[KQEMU]], [[VirtualBox]], and [[Xen]].
 
The introduction of the AMD-V and Intel VT-x instruction sets in 2005 allows x86 processors to meet the Popek and Goldberg virtualization requirements.<ref>{{cite conference
  | first = Keith
  | last = Adams
  | coauthors = and Agesen, Ole
  | title = A Comparison of Software and Hardware Techniques for x86 Virtualization
  | booktitle = Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, CA, USA, 2006
  | date = 2006-21-2006
  | url = http://www.vmware.com/pdf/asplos235_adams.pdf
  | id = ACM 1-59593-451-0/06/0010
  | accessdate = 2006-12-22 }}</ref>
 
==See also==
{{Div col||25em}}
* [[Itanium]]
* [[PowerPC]]
* [[Input/Output Base Address]]
* [[Interrupt request]]
* [[x86 assembly language]]
* [[x86 instruction listings]]
* [[List of AMD microprocessors]]
* [[List of Intel microprocessors]]
* [[List of VIA microprocessors]]
* [[List of x86 manufacturers]]
* [[Microarchitecture]]
{{Div col end}}
 
==Notes==
{{Notelist|30em}}
 
==References==
{{reflist|colwidth=30em}}
 
== Further reading ==
{{Refbegin}}
* {{cite conference
  | first = Mendel
  | last = Rosenblum
  | coauthors = and Garfinkel, Tal
  | title = Virtual machine monitors: current technology and future trends
  | booktitle = IEEE Computer, volume 38, issue 5
  | date = May 2005
  | url = http://ieeexplore.ieee.org/iel5/2/30853/01430630.pdf?tp=&isnumber=&arnumber=1430630
  }}
{{Refend}}
 
==External links==
{{Commons category|X86 Microprocessors}}
* [http://www.intel.com/museum/corporatetimeline/index.htm?iid=about+ln_history 25 Years of Intel Architecture]
* [http://www.x86-guide.com/ x86 CPUs guide]
* [http://www.itworld.com/it-management/346559/why-intel-cant-seem-retire-x86 Why Intel can't seem to retire the x86]
 
{{X86 assembly topics}}
{{Multimedia extensions}}
 
[[Category:1978 introductions]]
[[Category:Intel products]]
[[Category:Instruction set architectures]]
[[Category:IBM PC compatibles]]
[[Category:X86 architecture| ]]

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