Polynomial long division

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A barrel shifter is a digital circuit that can shift a data word by a specified number of bits in one clock cycle. It can be implemented as a sequence of multiplexers (mux.), and in such an implementation the output of one mux is connected to the input of the next mux in a way that depends on the shift distance.

For example, take a four-bit barrel shifter, with inputs A, B, C and D. The shifter can cycle the order of the bits ABCD as DABC, CDAB, or BCDA; in this case, no bits are lost. That is, it can shift all of the outputs up to three positions to the right (and thus make any cyclic combination of A, B, C and D). The barrel shifter has a variety of applications, including being a useful component in microprocessors (alongside the ALU).

Implementation

A barrel shifter is often implemented as a cascade of parallel 2×1 multiplexers. For a four-bit barrel shifter, an intermediate signal is used which shifts by two bits, or passes the same data, based on the value of S[1]. This signal is then shifted by another multiplexer, which is controlled by S[0]:

 im  = IN, if S[1] == 0
     = IN << 2, if S[1] == 1
 OUT = im, if S[0] == 0
     = im << 1, if S[0] == 1

Larger barrel shifters have additional stages.

Cost

The number of multiplexers required for an n-bit word is nlog2n. Five common word sizes and the number of multiplexers needed are listed below:

Cost of critical path in FO4 (estimated, without wire delay):

  • 32-bit: from 18 FO4 to 14 FO4[1]

Uses

A common usage of a barrel shifter is in the hardware implementation of floating-point arithmetic. For a floating-point add or subtract operation, the significands of the two numbers must be aligned, which requires shifting the smaller number to the right, increasing its exponent, until it matches the exponent of the larger number. This is done by subtracting the exponents, and using the barrel shifter to shift the smaller number to the right by the difference, in one cycle. If a simple shifter were used, shifting by n bit positions would require n clock cycles.

See also

External links

References

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