Multilateration: Difference between revisions

Latest revision as of 00:12, 3 November 2014

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-{{About|XOR in the sense of an electronic logic gate (e.g. CMOS 4030)|XOR in the purely logical sense|Exclusive disjunction|other uses|XOR (disambiguation)}}
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-{| class="wikitable" align=right
-|- bgcolor="#ddeeff" align="center"
-|colspan=2|'''INPUT'''<br>A &nbsp; B || '''OUTPUT'''<br> A XOR B
-|- bgcolor="#ddffdd" align="center"
-|0 || 0 || 0
-|- bgcolor="#ddffdd" align="center"
-|0 || 1 || 1
-|- bgcolor="#ddffdd" align="center"
-|1 || 0 || 1
-|- bgcolor="#ddffdd" align="center"
-|1 || 1 || 0
-|}
-The '''XOR gate''' (sometimes '''EOR gate''', or '''EXOR gate''') is a digital [[logic gate]] that implements an  [[exclusive or]]; that is, a true output (1/HIGH) results if one, and only one, of the inputs to the gate is true. If both inputs are false (0/LOW) or both are true, a false output results.  XOR represents the inequality function, i.e., the output is true if the inputs are not alike otherwise the output is false. A way to remember XOR is "one or the other but not both".
-XOR can also be viewed as addition modulo 2.  As a result, XOR gates are used to implement binary addition in computers.  A [[half adder]] consists of an XOR gate and an [[AND gate]].
-The [[Boolean algebra|algebraic expressions]] <math>A \cdot \overline{B} + \overline{A} \cdot B</math> and <math>(A + B) \cdot \overline{A \cdot B}</math> both represent the XOR gate with inputs ''A'' and ''B''. The behavior of XOR is summarized in the [[truth table]] shown on the right.
-{{Clear}}
-[[File:CMOS XOR Gate.svg|thumb|CMOS XOR gate]]
-==Symbols==
-There are two symbols for XOR gates: the traditional symbol and the [[Institute_of_Electrical_and_Electronics_Engineers|IEEE]] symbol. For more information see [[Logic gate#Symbols|Logic Gate Symbols]].
-[[Image:XOR ANSI.svg|frame|100px|left|Traditional XOR Symbol]][[Image:XOR IEC.svg|frame|100px|left|IEEE XOR Symbol]]
-{{Clear}}
-The [[List of logic symbols|logic symbols]] ⊕ and {{Unicode|⊻}} can be used to denote XOR in algebraic expressions.
-[[C programming language|C-like languages]] use the [[Caret#Programming languages|caret]] symbol '''^''' to denote bitwise XOR. (Note that the caret does not denote [[logical conjunction]] (AND) in these languages, despite the similarity of symbol.)
-==Transmission-Gate-Logic Wiring==
-An XOR gate can be constructed using [[MOSFET]]s. Here is a diagram of the transmission gate implementation of an XOR Gate.
-[[File:TransmissionCmosXORGate.png|thumb|561px|center|Transmission Gate Logic wiring of an XOR gate]]
-Note: The `Rss` resistor prevents shunting current directly from "A" and "B" to the output. Without it, if the circuit that provides inputs A and B does not have the proper driving capability, the output might not swing rail to rail or be severely slew-rate limited.
-==Alternatives==
-If a specific type of gate is not available, a circuit that implements the same function can be constructed from other available gates. A circuit implementing an XOR function can be trivially constructed from an XNOR gate followed by a NOT gate. If we consider the expression <math>A \cdot \overline{B} + \overline{A} \cdot B</math>, we can construct an XOR gate circuit directly using AND, OR and NOT gates. However, this approach requires five gates of three different kinds.
-An XOR gate circuit can be made from four NAND or five NOR gates in the configurations shown below                                                                                      . In fact, both NAND and NOR gates are so-called "universal gates," and any logical function can be constructed from either [[NAND logic]] or [[NOR logic]] alone.
-{| style="text-align:center; margin: 1em auto 1em auto"
-|[[image:XOR from NAND.svg|frame|right|XOR gate circuit constructed using only NAND gates.]]
-[[image:XOR from NOR.svg|frame|right|XOR gate circuit constructed using only NOR gates.]]
-|}
-<br clear="both" />
-==More than two inputs==
-Strict reading of the definition of [[exclusive or]], or observation of the IEC rectangular symbol, raises the question of correct behaviour with additional inputs.  If a logic gate were to accept three or more inputs and produce a true output if exactly one of those inputs were true, then it would in effect be a [[one-hot]] detector (and indeed this is the case for only two inputs).  However, it is rarely implemented this way in practice.
-It is most common to regard subsequent inputs as being applied through a cascade of binary exclusive-or operations: the first two signals are fed into an XOR gate, then the output of that gate is fed into a second XOR gate together with the third signal, and so on for any remaining signals.  The result is a circuit that outputs a 1 when the number of 1s at its inputs is odd, and a 0 when the number of incoming 1s is even.  This makes it practically useful as a [[parity (telecommunication)|parity generator]] or a modulo-2 [[adder (electronics)|adder]].
-For example, the 74LVC1G386 microchip is advertised as a three-input logic gate, and implements a parity generator.<ref name="74LVC1G386">[http://www.nxp.com/documents/data_sheet/74LVC1G386.pdf 74LVC1G386] [[data sheet]]</ref>
-==Applications==
-===Uses in addition===
-The XOR logic gate can be used as a one-bit [[adder (electronics)|adder]] that adds any two bits together to output one bit. For example, if we add '''1''' plus '''1''' in [[Binary numeral system|binary]], we expect a two-bit answer, '''10''' (i.e. '''2''' in decimal). Since the trailing ''sum'' bit in this output is achieved with XOR, the preceding ''carry'' bit is calculated with an [[AND gate]]. This is the main principle in [[Adder (electronics)#Half adder|Half Adders]] and the combined AND-XOR circuit may be chained together in order to add ever longer binary numbers.[[File:Half Adder.svg|right|frame|Example half adder circuit diagram]]
-===Pseudo-random number generation===
-Pseudo-random number (PRN) generators, specifically '''[[Linear feedback shift register]]s''', are defined in terms of the exclusive-or operation. Hence, a suitable setup of XOR gates can model a linear feedback shift register, in order to generate random sequences of bits.
-===Correlation and sequence detection===
-XOR gates produce a '''0''' when both inputs match.  When searching for a specific bit pattern or PRN sequence in a very long data sequence, a series of XOR gates can be used to compare a string of bits from the data sequence against the target sequence in parallel.  The number of '''0''' outputs can then be counted to determine how well the data sequence matches the target sequence.  Correlators are used in many communications devices such as [[CDMA]] receivers and decoders for error correction and channel codes.  In a CDMA receiver, correlators are used to extract the polarity of a specific PRN sequence out of a combined collection of PRN sequences.
-A correlator looking for '''11010''' in the data sequence '''1110100101''' would compare the incoming data bits against the target sequence at every possible offset while counting the number of matches (zeros):
- 1110100101 (data)
-      (target)
-      (XOR) 2 zero bits
- 1110100101
-     5 zero bits
- 1110100101
-    2 zero bits
- 1110100101
-   2 zero bits
- 1110100101
-  4 zero bits
- 1110100101
-0 zero bits
- Matches by offset:
-   .
-   :     :
- : : : : :
- -----------
-1 2 3 4 5
-In this example, the best match occurs when the target sequence is offset by 1 bit and all five bits match.  When offset by 5 bits, the sequence exactly matches its inverse.  By looking at the difference between the number of ones and zeros that come out of the bank of XOR gates, it is easy to see where the sequence occurs and whether or not it is inverted.  Longer sequences are easier to detect than short sequences.
-==See also==
-*[[Exclusive or]]
-*[[AND gate]]
-*[[OR gate]]
-*[[NOT gate]]
-*[[NAND gate]]
-*[[NOR gate]]
-*[[XNOR gate]]
-*[[Boolean algebra (logic)]]
-*[[Logic gates]]
-{{Commons category|XOR gates}}
-{{Logical connectives}}
-==External links==
-* [http://teahlab.com/xor_gate/ Interactive XOR Gate], Demonstrate the logic flow of the XOR Gate circuit created with Teahlab's simulator.
-==References==
-{{Reflist}}
-{{DEFAULTSORT:Xor Gate}}
-[[Category:Logic gates]]
-[[sv:Disjunktion (logik)#OR-grind och XOR-grind]]

Multilateration: Difference between revisions

Latest revision as of 00:12, 3 November 2014

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